|
| 1 | +''' |
| 2 | +========================================================================= |
| 3 | +GlobalReduceUnitRTL_test.py |
| 4 | +========================================================================= |
| 5 | +Simple test for GlobalReduceUnitRTL. |
| 6 | +
|
| 7 | +Author : Cheng Tan |
| 8 | + Date : Sep 8, 2025 |
| 9 | +''' |
| 10 | + |
| 11 | +from pymtl3.stdlib.test_utils import config_model_with_cmdline_opts |
| 12 | + |
| 13 | +from ..GlobalReduceUnitRTL import GlobalReduceUnitRTL |
| 14 | +from ...lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL |
| 15 | +from ...lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL |
| 16 | +from ...lib.cmd_type import * |
| 17 | +from ...lib.messages import * |
| 18 | +from ...lib.opt_type import * |
| 19 | + |
| 20 | +#------------------------------------------------------------------------- |
| 21 | +# TestHarness |
| 22 | +#------------------------------------------------------------------------- |
| 23 | + |
| 24 | +class TestHarness(Component): |
| 25 | + |
| 26 | + def construct(s, DataType, InterCgraPktType, ControllerXbarPktType, |
| 27 | + input_count, input_data, expected_output): |
| 28 | + |
| 29 | + s.src_count = TestSrcRTL(InterCgraPktType, input_count) |
| 30 | + s.src_data = TestSrcRTL(InterCgraPktType, input_data) |
| 31 | + |
| 32 | + s.sink = TestSinkRTL(ControllerXbarPktType, expected_output) |
| 33 | + |
| 34 | + s.dut = GlobalReduceUnitRTL(DataType, |
| 35 | + InterCgraPktType, |
| 36 | + ControllerXbarPktType) |
| 37 | + |
| 38 | + # Connections |
| 39 | + s.dut.recv_count //= s.src_count.send |
| 40 | + s.dut.recv_data //= s.src_data.send |
| 41 | + s.dut.send //= s.sink.recv |
| 42 | + |
| 43 | + def done(s): |
| 44 | + return s.src_count.done() and \ |
| 45 | + s.src_data.done() and \ |
| 46 | + s.sink.done() |
| 47 | + |
| 48 | + def line_trace(s): |
| 49 | + return s.dut.line_trace() |
| 50 | + |
| 51 | +#------------------------------------------------------------------------- |
| 52 | +# run_rtl_sim |
| 53 | +#------------------------------------------------------------------------- |
| 54 | + |
| 55 | +def run_sim(test_harness, max_cycles = 100): |
| 56 | + |
| 57 | + # Creates a simulator. |
| 58 | + test_harness.elaborate() |
| 59 | + test_harness.apply(DefaultPassGroup()) |
| 60 | + test_harness.sim_reset() |
| 61 | + |
| 62 | + # Runs simulation. |
| 63 | + ncycles = 0 |
| 64 | + print() |
| 65 | + print("{}:{}".format(ncycles, test_harness.line_trace())) |
| 66 | + while not test_harness.done() and ncycles < max_cycles: |
| 67 | + test_harness.sim_tick() |
| 68 | + ncycles += 1 |
| 69 | + print("{}:{}".format(ncycles, test_harness.line_trace())) |
| 70 | + |
| 71 | + # Checks timeout. |
| 72 | + assert ncycles < max_cycles |
| 73 | + |
| 74 | + test_harness.sim_tick() |
| 75 | + test_harness.sim_tick() |
| 76 | + test_harness.sim_tick() |
| 77 | + |
| 78 | +#------------------------------------------------------------------------- |
| 79 | +# Test cases |
| 80 | +#------------------------------------------------------------------------- |
| 81 | + |
| 82 | +def test_simple(cmdline_opts): |
| 83 | + data_nbits = 32 |
| 84 | + predicate_nbits = 1 |
| 85 | + |
| 86 | + num_cgra_columns = 4 |
| 87 | + num_cgra_rows = 1 |
| 88 | + num_cgras = num_cgra_columns * num_cgra_rows |
| 89 | + num_tiles = 4 |
| 90 | + num_rd_tiles = 3 |
| 91 | + cgra_id_nbits = clog2(num_cgras) |
| 92 | + ControllerIdType = mk_bits(cgra_id_nbits) |
| 93 | + ctrl_mem_size = 16 |
| 94 | + num_fu_inports = 2 |
| 95 | + num_fu_outports = 2 |
| 96 | + num_tile_inports = 4 |
| 97 | + num_tile_outports = 4 |
| 98 | + data_mem_size_global = 16 |
| 99 | + addr_nbits = clog2(data_mem_size_global) |
| 100 | + num_registers_per_reg_bank = 16 |
| 101 | + cgra_id = 0 |
| 102 | + |
| 103 | + idTo2d_map = { |
| 104 | + 0: [0, 0], |
| 105 | + 1: [1, 0], |
| 106 | + 2: [2, 0], |
| 107 | + 3: [3, 0] |
| 108 | + } |
| 109 | + |
| 110 | + controller2addr_map = { |
| 111 | + 0: [0, 3], |
| 112 | + 1: [4, 7], |
| 113 | + 2: [8, 11], |
| 114 | + 3: [12, 15], |
| 115 | + } |
| 116 | + |
| 117 | + DataType = mk_data(data_nbits, predicate_nbits) |
| 118 | + DataAddrType = mk_bits(addr_nbits) |
| 119 | + |
| 120 | + CtrlType = mk_ctrl(num_fu_inports, |
| 121 | + num_fu_outports, |
| 122 | + num_tile_inports, |
| 123 | + num_tile_outports, |
| 124 | + num_registers_per_reg_bank) |
| 125 | + |
| 126 | + CtrlAddrType = mk_bits(clog2(ctrl_mem_size)) |
| 127 | + |
| 128 | + CgraPayloadType = mk_cgra_payload(DataType, |
| 129 | + DataAddrType, |
| 130 | + CtrlType, |
| 131 | + CtrlAddrType) |
| 132 | + |
| 133 | + InterCgraPktType = mk_inter_cgra_pkt(num_cgra_columns, |
| 134 | + num_cgra_rows, |
| 135 | + num_tiles, |
| 136 | + num_rd_tiles, |
| 137 | + CgraPayloadType) |
| 138 | + |
| 139 | + ControllerXbarPktType = mk_controller_noc_xbar_pkt(InterCgraPktType) |
| 140 | + |
| 141 | + input_count = [ |
| 142 | + InterCgraPktType(payload = CgraPayloadType(CMD_GLOBAL_REDUCE_COUNT, data = DataType(3, 0, 0, 0))), |
| 143 | + ] |
| 144 | + |
| 145 | + input_data = [ |
| 146 | + # src dst src_x src_y dst_x dst_y src_tile_id dst_tile_id |
| 147 | + InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, data = DataType(2, 1, 0, 0))), |
| 148 | + InterCgraPktType(0, 1, 0, 0, 1, 0, 2, 4, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, data = DataType(4, 1, 0, 0))), |
| 149 | + InterCgraPktType(0, 2, 0, 0, 2, 0, 3, 4, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, data = DataType(6, 1, 0, 0))), |
| 150 | + InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, data = DataType(3, 1, 0, 0))), |
| 151 | + InterCgraPktType(0, 1, 0, 0, 1, 0, 2, 4, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, data = DataType(5, 1, 0, 0))), |
| 152 | + InterCgraPktType(0, 2, 0, 0, 2, 0, 3, 4, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD, data = DataType(7, 1, 0, 0))), |
| 153 | + InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, data = DataType(3, 1, 0, 0))), |
| 154 | + InterCgraPktType(0, 1, 0, 0, 1, 0, 2, 4, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, data = DataType(5, 1, 0, 0))), |
| 155 | + InterCgraPktType(0, 2, 0, 0, 2, 0, 3, 4, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_MUL, data = DataType(7, 1, 0, 0))), |
| 156 | + ] |
| 157 | + |
| 158 | + expected_output = [ |
| 159 | + # Reversed src/dst. |
| 160 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD_RESPONSE, data = DataType(12, 1, 0, 0)))), |
| 161 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(1, 0, 1, 0, 0, 0, 4, 2, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD_RESPONSE, data = DataType(12, 1, 0, 0)))), |
| 162 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(2, 0, 2, 0, 0, 0, 4, 3, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD_RESPONSE, data = DataType(12, 1, 0, 0)))), |
| 163 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD_RESPONSE, data = DataType(15, 1, 0, 0)))), |
| 164 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(1, 0, 1, 0, 0, 0, 4, 2, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD_RESPONSE, data = DataType(15, 1, 0, 0)))), |
| 165 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(2, 0, 2, 0, 0, 0, 4, 3, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_ADD_RESPONSE, data = DataType(15, 1, 0, 0)))), |
| 166 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_MUL_RESPONSE, data = DataType(105, 1, 0, 0)))), |
| 167 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(1, 0, 1, 0, 0, 0, 4, 2, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_MUL_RESPONSE, data = DataType(105, 1, 0, 0)))), |
| 168 | + ControllerXbarPktType(inter_cgra_pkt = InterCgraPktType(2, 0, 2, 0, 0, 0, 4, 3, payload = CgraPayloadType(CMD_GLOBAL_REDUCE_MUL_RESPONSE, data = DataType(105, 1, 0, 0)))), |
| 169 | + ] |
| 170 | + |
| 171 | + th = TestHarness(DataType, |
| 172 | + InterCgraPktType, |
| 173 | + ControllerXbarPktType, |
| 174 | + input_count, |
| 175 | + input_data, |
| 176 | + expected_output) |
| 177 | + th.elaborate() |
| 178 | + th = config_model_with_cmdline_opts(th, cmdline_opts, duts = ['dut']) |
| 179 | + run_sim(th) |
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