Update README.md

Author: themperek

README.md

@@ -5,6 +5,8 @@
 
 SpiceBind is a lightweight bridge that enables co-simulation of **analog [ngspice](https://ngspice.sourceforge.io/)** circuits alongside **HDL simulators**. This tool allows design engineers to seamlessly integrate SPICE-accurate analog models into their existing digital verification flows.
 
+⚠️ **Note**: This is an early release. We welcome feedback and contributions from the community.
+
 ### Key Benefits
 
 - **Preserve Your Existing Flow**: Keep your RTL, testbenches, and waveform viewers unchanged
@@ -22,8 +24,6 @@ Perfect for ASIC designers working on:
 - Power management units
 - Sensor interfaces and analog front-ends
 
-⚠️ **Note**: This is an early release. We welcome feedback and contributions from the community.
-
 ## How It Works
 
 SpiceBind enables you to write Verilog source code that includes an empty Verilog module and have it implemented by ngspice. Here's how the magic happens: