Fix SPLL as well

Author: jamesmunns

embassy-mcxa/src/clocks/config.rs

@@ -133,7 +133,6 @@ pub struct ClocksConfig {
     #[cfg(not(feature = "sosc-as-gpio"))]
     pub sosc: Option<SoscConfig>,
     /// SPLL
-    #[cfg(feature = "mcxa2xx")]
     pub spll: Option<SpllConfig>,
 }
 
@@ -294,7 +293,6 @@ pub enum MainClockSource {
     #[cfg(all(feature = "mcxa5xx", not(feature = "rosc-32k-as-gpio")))]
     RoscOsc32K,
     /// Clock derived from `pll1_clk`, via the internal PLL
-    #[cfg(feature = "mcxa2xx")]
     SPll1,
 }
 
@@ -352,6 +350,7 @@ pub enum SpllSource {
     /// Fast Internal Oscillator (45MHz)
     // NOTE: Figure 69 says "firc_45mhz"/"clk_45m", not "fro_hf_gated",
     // so this is is always 45MHz.
+    #[cfg(feature = "mcxa2xx")]
     Firc,
     /// S Internal Oscillator (12M)
     Sirc,
@@ -673,7 +672,6 @@ impl Default for ClocksConfig {
             osc32k: None,
             #[cfg(not(feature = "sosc-as-gpio"))]
             sosc: None,
-            #[cfg(feature = "mcxa2xx")]
             spll: None,
         }
     }

embassy-mcxa/src/clocks/mod.rs

@@ -50,20 +50,20 @@ use periph_helpers::{PreEnableParts, SPConfHelper};
 use crate::chips::{ClockLimits, clock_limits};
 use crate::pac;
 use crate::pac::cmc::vals::CkctrlCkmode;
-use crate::pac::scg::vals::{Erefs, Range, Scs, SirccsrLk, Sircerr, Sircvld, SosccsrLk, Soscerr};
-#[cfg(feature = "mcxa2xx")]
 use crate::pac::scg::vals::{
-    Fircacc, FircaccIe, FirccsrLk, Fircerr, FircerrIe, Fircsten, Fircvld, FreqSel, Source, SpllLock, SpllcsrLk,
-    Spllerr, Spllsten, TrimUnlock,
+    Erefs, Range, Scs, SirccsrLk, Sircerr, Sircvld, SosccsrLk, Soscerr, Source, SpllLock, SpllcsrLk, Spllerr, Spllsten,
+    TrimUnlock,
 };
+#[cfg(feature = "mcxa2xx")]
+use crate::pac::scg::vals::{Fircacc, FircaccIe, FirccsrLk, Fircerr, FircerrIe, Fircsten, Fircvld, FreqSel};
 use crate::pac::spc::vals::{
     ActiveCfgBgmode, ActiveCfgCoreldoVddDs, ActiveCfgCoreldoVddLvl, LpCfgBgmode, LpCfgCoreldoVddLvl, Vsm,
 };
-use crate::pac::syscon::vals::{AhbclkdivUnstab, FrolfdivHalt, FrolfdivReset, FrolfdivUnstab};
-#[cfg(feature = "mcxa2xx")]
 use crate::pac::syscon::vals::{
-    FrohfdivHalt, FrohfdivReset, FrohfdivUnstab, Pll1clkdivHalt, Pll1clkdivReset, Pll1clkdivUnstab,
+    AhbclkdivUnstab, FrolfdivHalt, FrolfdivReset, FrolfdivUnstab, Pll1clkdivHalt, Pll1clkdivReset, Pll1clkdivUnstab,
 };
+#[cfg(feature = "mcxa2xx")]
+use crate::pac::syscon::vals::{FrohfdivHalt, FrohfdivReset, FrohfdivUnstab};
 pub mod config;
 pub mod periph_helpers;
 
@@ -134,7 +134,6 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> {
 
     #[cfg(not(feature = "sosc-as-gpio"))]
     operator.configure_sosc()?;
-    #[cfg(feature = "mcxa2xx")]
     operator.configure_spll()?;
 
     // Finally, setup main clock
@@ -314,7 +313,6 @@ unsafe fn restart_active_only_clocks(_cs: &CriticalSection) {
     }
 
     // Ensure SPLL is up and running
-    #[cfg(feature = "mcxa2xx")]
     if let Some(spll) = clocks.pll1_clk.as_ref()
         && !matches!(spll.power, PoweredClock::AlwaysEnabled)
     {
@@ -490,11 +488,9 @@ pub struct Clocks {
     pub cpu_system_clk: Option<Clock>,
 
     /// `pll1_clk` is the output of the main system PLL, `pll1`.
-    #[cfg(feature = "mcxa2xx")]
     pub pll1_clk: Option<Clock>,
 
     /// `pll1_clk_div` is a configurable frequency clock, sourced from `pll1_clk`
-    #[cfg(feature = "mcxa2xx")]
     pub pll1_clk_div: Option<Clock>,
 }
 
@@ -871,14 +867,12 @@ impl Clocks {
     }
 
     /// Ensure the `pll1_clk` clock is active and valid at the given power state.
-    #[cfg(feature = "mcxa2xx")]
     #[inline]
     pub fn ensure_pll1_clk_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
         self.ensure_clock_active(&self.pll1_clk, "pll1_clk", at_level)
     }
 
     /// Ensure the `pll1_clk_div` clock is active and valid at the given power state.
-    #[cfg(feature = "mcxa2xx")]
     #[inline]
     pub fn ensure_pll1_clk_div_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
         self.ensure_clock_active(&self.pll1_clk_div, "pll1_clk_div", at_level)
@@ -1706,7 +1700,6 @@ impl ClockOperator<'_> {
         Ok(())
     }
 
-    #[cfg(feature = "mcxa2xx")]
     fn configure_spll(&mut self) -> Result<(), ClockError> {
         // # Vocab
         //
@@ -1740,6 +1733,7 @@ impl ClockOperator<'_> {
                 .as_ref()
                 .map(|c| (c, Source::SOSC))
                 .ok_or("sosc not active"),
+            #[cfg(feature = "mcxa2xx")]
             config::SpllSource::Firc => self
                 .clocks
                 .clk_45m
@@ -2094,7 +2088,6 @@ impl ClockOperator<'_> {
             MainClockSource::RoscFro16K => (Scs::ROSC, "fro16k", self.clocks.clk_16k_vdd_core.as_ref()),
             #[cfg(all(feature = "mcxa5xx", not(feature = "rosc-32k-as-gpio")))]
             MainClockSource::RoscOsc32K => (Scs::ROSC, "osc32k", self.clocks.clk_32k_vdd_core.as_ref()),
-            #[cfg(feature = "mcxa2xx")]
             MainClockSource::SPll1 => (Scs::SPLL, "pll1_clk", self.clocks.pll1_clk.as_ref()),
         };
         let Some(main_clk_src) = clk else {

embassy-mcxa/src/clocks/periph_helpers/mod.rs

@@ -305,7 +305,6 @@ pub enum CTimerClockSel {
     /// clk_1m/FRO_LF divided by 12
     Clk1M,
     /// Internal PLL output, with configurable divisor
-    #[cfg(feature = "mcxa2xx")]
     Pll1ClkDiv,
     /// Disabled
     None,
@@ -399,10 +398,16 @@ impl SPConfHelper for CTimerConfig {
 
                 (freq, mux)
             }
-            #[cfg(feature = "mcxa2xx")]
             CTimerClockSel::Pll1ClkDiv => {
                 let freq = clocks.ensure_pll1_clk_div_active(&self.power)?;
-                (freq, CtimerClkselMux::CLKROOT_FUNC_6)
+
+                // TODO: fix PAC names for consistency
+                #[cfg(feature = "mcxa2xx")]
+                let mux = CtimerClkselMux::CLKROOT_FUNC_6;
+                #[cfg(feature = "mcxa5xx")]
+                let mux = CtimerClkselMux::I6_CLKROOT_SPLL_DIV;
+
+                (freq, mux)
             }
             CTimerClockSel::None => {
                 // no ClkrootFunc7, just write manually for now

examples/mcxa5xx/src/bin/blinky-spll.rs

@@ -0,0 +1,57 @@
+//! Similar to blinky, but clocked with external SOSC
+//!
+//! This will probably go away once we have the CLKOUT peripheral supported.
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::PoweredClock;
+use embassy_mcxa::clocks::config::{MainClockSource, SpllConfig, SpllMode, SpllSource};
+use embassy_time::Timer;
+use hal::gpio::{DriveStrength, Level, Output, SlewRate};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.spll = Some(SpllConfig {
+        source: SpllSource::Sirc,
+        // 12MHz
+        // 12 x 32 => 384MHz
+        // 384 / (16 x 2) => 12.0MHz
+        mode: SpllMode::Mode1b {
+            m_mult: 32,
+            p_div: 16,
+            bypass_p2_div: false,
+        },
+        power: PoweredClock::NormalEnabledDeepSleepDisabled,
+        pll1_clk_div: None,
+    });
+    cfg.clock_cfg.main_clock.source = MainClockSource::SPll1;
+    let p = hal::init(cfg);
+
+    defmt::info!("Blink example");
+
+    let mut red = Output::new(p.P2_14, Level::High, DriveStrength::Normal, SlewRate::Fast);
+    let mut green = Output::new(p.P2_22, Level::High, DriveStrength::Normal, SlewRate::Fast);
+    let mut blue = Output::new(p.P2_23, Level::High, DriveStrength::Normal, SlewRate::Fast);
+
+    loop {
+        defmt::info!("Toggle LEDs");
+
+        red.toggle();
+        Timer::after_millis(250).await;
+
+        red.toggle();
+        green.toggle();
+        Timer::after_millis(250).await;
+
+        green.toggle();
+        blue.toggle();
+        Timer::after_millis(250).await;
+        blue.toggle();
+
+        Timer::after_millis(250).await;
+    }
+}