Is it possible to skip using asap 7 calibre deck to perform synthesis?

[Waxpple]

Hi,

I want to ask a few questions about using hammer with the chipyard.

1. Is it possible to skip using asap 7 calibre deck to perform synthesis?
   make buildfile needs the deck file.
   *I use .edu instead of .edu.tw email to request the Calibre deck and still no response yet.
2. Is it possible to use primetime to calculate the netlist power?
3. When I simply type make buildfile under vlsi/. It will say that it cannot compile the memory.
   

For now, I just want to synthesize the design and calculate its netlist simulation performance.

Thank you.
Best regards,
Waxpple

[harrisonliew]

1. Yes, you can synthesize without the Calibre decks. You will need to comment this out: https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/defaults.yml#L4 so that Hammer doesn't try to extract/check the tarball. I don't know what's going on with the ASU folks. The developer Vinay's email is vinay.vashishtha@asu.edu but I believe he left ASU already and I don't know who has taken over the.
2. We do not have a PrimeTime Hammer plugin, but if you have scripts yourself you can of course take the outputs from Hammer into your flow. We would also appreciate any contributions for a PrimeTime plugin!
3. This is actually an output from MacroCompiler, and it seems like you have a memory that requires mask granularity of 17 and an error (it probably should just be a warning) is thrown for each available SRAM that doesn't match that mask width. Does it fail entirely, or do you still get a .mems.v file at the end?

[Waxpple]

Hi,

1. I commented out line 4
   (https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/defaults.yml#L4)
   and It will still enter the deck file extraction.
   (a) Shouldn't line 6 and 9 use technology.asap7.pdk_install_dir and technology.asap7.stdcell_install_dir directly? (

   hammer/src/hammer-vlsi/technology/asap7/defaults.yml

   Lines 5 to 9 in d200c62

   	# Path to the directory containing the PDK files
   	pdk_install_dir: "${technology.asap7.tarball_dir}/asap7PDK_r1p7"
   	pdk_install_dir_meta: lazysubst
   	# Path to the directory containing the standard cell collateral
   	stdcell_install_dir: "${technology.asap7.tarball_dir}/asap7sc7p5t_27"

   )
   (b) After commented asap7/defaults.yml #L4, the program still enter this condition

   hammer/src/hammer-tech/hammer_tech.py

   Lines 741 to 742 in d200c62

   	if self.config.tarballs is not None:
   	self.extract_tarballs()

   and call extract_tallballs. I commented L742 for ad hoc and it works now.
   (c) Yes, I also post an issue on Vinay's asap repository too.
2. Yes! I love to contribute something. After I figure the flow all out, I will try to implement the primetime plugin.
3. Yes, the vlsi/generated-src/{Design_name}/{Design_name}.harness.mems.v exists.
4. Is there any way to perform netlist-sim with vcs and output log file in output/ like I do in rtl-sim make run-asm-tests. Because if I perform netlist-sim, vcs only shows simulation completed without telling it is correct or not.

Thanks!

[harrisonliew]

1. Ooops, I realized that you should have actually removed these lines: https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/asap7.tech.json#L19-L25. This is what the lines 741-742 actually check to extract. This way you don't need to modify defaults.yml at all.
2. Thank you so much! If you want to interface directly with me for any questions about writing the plugin, you can email me at harrisonliew@berkeley.edu
3. Ok, what about vlsi/generated-src/{Design_name}/{Design_name}.top.mems.v file? This is what would be needed in order to run synthesis. If this exists, then MacroCompiler was able to compile some memories.
4. Assuming you are running this with Chipyard, yes, you can run netlist (RTL-level) sim with Hammer and VCS. You will need to use the sim-rtl-debug target here: https://github.com/ucb-bar/chipyard/blob/eb48397009c7708d2c43b02ac1da2193ab1df25e/vlsi/sim.mk#L53 with the appropriate benchmark set in the BINARY variable. Then, you will get the debug output (all instructions + a VPD/FSDB file) in the sim-rundir.

[Waxpple]

Hi,

3. Not sure if my thought is correct, the memory compiler should generate .v for simulation of the memory behavior, .gds and .lef for APR and its timing library like .lib.
   What should this folder vlsi/generated-src/{Design_name}/sram_generator-rundir do, is it normal to be empty?
   Under vlsi/generated-src/{Design_name}/tech-asap7-cache there is SRAM with .lib, .gds, and .lib files.

With chipyard, the macro compiler is using Barstools right? Barstools.
As you mentioned, maybe it is just a warning.

Thanks.

[harrisonliew]

Yes, the macro compiler is using Barstools.

So, in the asap7 case, its sram compiler puts one of the collateral (.lib) in the tech-asap7-cache directory

hammer/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py

Line 40 in d200c62

lib_path ="{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str)

, then generates a JSON file (sram_generator-output.json) that points to all of these files

hammer/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py

Line 43 in d200c62

lib = ExtraLibrary(prefix=None, library=Library(

. As long as you have this resulting JSON file and the memories inside match the ones in vlsi/generated-src/{Design_name}/{Design_name}.top.mems.v, you are good to go. Not all tech plugins utilize the sram_generator-rundir.

[Waxpple]

Hi,

1. I have synthesized LargeBoomConfig, and even I push Genus very hard to optimize the design, the timing is still not met in the default sdc.

...
set_db syn_generic_effort high
set_db syn_map_effort high
set_db syn_opt_effort extreme
...
syn_opt
syn_opt -inc
...

*Note: This still ends up with better timing even it is not met. Maybe in the flow, it can add an option on effort strategy.

I think It will also fail on post-synthesis simulation too. But I run rtl-sim-debug, It will only generate a waveform file. and in the terminal, there is a Fatal keyword.

How to generate a result such as this in rtl-sim?

2. Where do I change the default sdc config?
3. I think vcs should use -fpg flag to take advantage of multi-thread simulation. The idea is from (https://www.francisz.cn/2020/07/09/vcs-parallel/)

[Leon924]

Hi, Waxpple:

Could you please tell me what your linux server version and VCS version is? I have some problem in make sim-rtl issued here. #643

Best,
Leon

[Waxpple]

Hi, Waxpple:

Could you please tell me what your linux server version and VCS version is? I have some problem in make sim-rtl issued here. #643

Best, Leon

Hi,

Yes, here is my environment set up.

OS: Redhat Enterprise Linux 7.9
VCS: 2021.09 version

I think the EDA tool is not very compatible with the Debian-based Linux system.

[Leon924]

Hi, Waxpple:
Could you please tell me what your linux server version and VCS version is? I have some problem in make sim-rtl issued here. #643
Best, Leon

Hi,

Yes, here is my environment set up.

OS: Redhat Enterprise Linux 7.9 VCS: 2021.09 version

I think the EDA tool is not very compatible with the Debian-based Linux system.

Thanks a lot.

Yes, There are some many problems need to fix. I will try it on another RHEL6.10 linux server.

[harrisonliew]

I have synthesized LargeBoomConfig, and even I push Genus very hard to optimize the design, the timing is still not met in the default sdc.

Perhaps a dumb question, but did you adjust the clock constraints (vlsi.inputs.clocks)? The default clock period is set for the example tiny config. Due to the size of a LargeBoomConfig, it would almost certainly not pass timing at the same frequency. Indeed, you can add these optimization commands as a synthesis hook in your flow (see the example-vlsi file for a template).

For your simulation, are you running timing-annotated simulation or only post-synthesis functional simulation? If it's timing-annotated, it would make sense that it doesn't pass. If not, then I might look at that line in the .top.v file to see where the $fatal directive is being called to debug. If this is a functional issue with BOOM, please raise an issue in the BOOM and/or Chipyard repositories, where appropriate instead of in Hammer.

I think vcs should use -fpg flag to take advantage of multi-thread simulation.

This would be a welcome contribution in hammer-synopsys-plugins! This should use the vlsi.core.max_threads key to set the number of cores.

I think the EDA tool is not very compatible with the Debian-based Linux system.

VCS 2021.09 should be compatible with RHEL7 (we use that here), but not RHEL6 (due to outdated GNU C libraries).

[Waxpple]

Update on the ASAP7 Calibre decks. I sent an email to the ASAP7 project leader asking for help, and he replied that the Calibre deck is pulled off from the site for now.

[harrisonliew]

Did he give any reason why? This is quite important for people wanting to use the PDK...

Anyways, I think I might actually implement the -fgp flags myself since it might potentially help me out. I'll have you review the PR when I'm done.

[harrisonliew]

I'd love for you to review the VCS parallelism PR: ucb-bar/hammer-synopsys-plugins#23 (I can't add you as a reviewer directly).

[Waxpple]

Did he give any reason why? This is quite important for people wanting to use the PDK...

Yes, there are some issues/concerns with files being distributed on GitHub.

I'd love for you to review the VCS parallelism PR: ucb-bar/hammer-synopsys-plugins#23 (I can't add you as a reviewer directly).

Sure!

I can run simulation under chipyard/sims/vcs with same CONFIG and BINARY. But I cannot run the make sim-rtl under chipyard/vlsi/. Which means it is not a functional error? Or I should post an issue on chipyard?

If I turn the dramsim off, the result is still the same.

/home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/simv +permissive +dramsim +dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +permissive-off /home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09_Full64; Runtime version S-2021.09_Full64;  Apr  2 03:41 2022
[UART] UART0 is here (stdin/stdout).
== Loading device model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' == 
== Loading system model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
Fatal: "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", 191091: TestDriver.testHarness.chiptop.system.tile_prci_domain.tile_reset_domain.boom_tile.frontend.icache: at time 2913500000 fs
$finish called from file "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", line 191091.
$finish at simulation time             29135000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2913500000 fs
CPU Time:      1.340 seconds;       Data structure size:  14.0Mb
Sat Apr  2 03:41:41 2022

The top Verilog file

 `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 <= 3'h1 | ~s1_valid) & ~reset) begin
          $fatal; // @[icache.scala 206:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_9 <= 3'h1 | ~s1_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at icache.scala:206 assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n"); // @[icache.scala 206:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS

[harrisonliew]

Yes, there are some issues/concerns with files being distributed on GitHub.

Weird. The whole point of requesting the decks was that it was not distributed on Github along with the rest of the PDK.

I can run simulation under chipyard/sims/vcs with same CONFIG and BINARY. But I cannot run the make sim-rtl under chipyard/vlsi/. Which means it is not a functional error? Or I should post an issue on chipyard?

Not quite. There is a difference between running RTL simulation in sims/vcs vs. in vlsi. In the latter case, you have replaced the SeqMems with the behavioral model of the ASAP7 SRAMs that are mapped to your design.

I haven't seen this particular issue before, and it looks like it has something to do with your ICache, not the simulated DRAM (hence why turning off DRAMSim didn't make a difference). Are you able to pull up the waveforms of both simulations to compare those wires (_T_9 and s1_valid, perhaps) to see if there's a difference that might be caused by the SRAM models in any way?