`find_regs_paths.json` not escape registers correctly, causing post-synthesis simulation to fail

[cedard234]

Background work

• Yes, I searched the documentation
• Yes, I searched in the Support (Q&A) section of the Discussions and read the posting guidelines
• Yes, I searched prior issues
• This issue is specific to Hammer, i.e., does not belong in a plugin repository instead
• My report does not contain sensitive info (e.g., PDK information under NDA)
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Hammer version and plugin hashes

Release: 1.0.0
Hash: a1b2c3

Other Setup

Using hammer environment to run synthesis using Cadence genus 23.1.

Current Behavior

Inside my find_regs_path.json generated in syn-rundir after running syn step, some registers are correctly escaped while others are not. Here is the code snippet from that file:

    "path": "dut_FD/\\counter_reg[1]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\counter_reg[2]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\counter_reg[3]",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[0]7",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[1]8",
    "pin": "q"
  },

This will cause issue when running post-synthesis simulation, because force_regs.ucli will try to use the unescaped name to perform initialization. This cause "object not found" error when running this step.

Expected Behavior

hammer is expected to be consistent with all registers, not sure why this only happen to some of these registers. The code from hammer/common/cadence/__init__.py looks good to me though.

    def process_reg_paths(self, path: str) -> bool:
        # Post-process the all_regs list here to avoid having too much logic in TCL
        with open(path, "r+") as f:
            reg_paths = json.load(f)
            output_paths = [] #  type: List[Dict[str,str]]
            assert isinstance(reg_paths, List), "Output find_regs_paths.json should be a json list of strings"
            for i in range(len(reg_paths)):
                split = reg_paths[i].split("/")
                print(split)
                # If the net is part of a generate block, the generated names have a "." in them and the whole name
                # needs to be escaped.
                for index, node in enumerate(split):
                    if "." in node:
                        split[index] = "\\" + node + "\\"
                # If the last net is part of a bus, it needs to be escaped
                if split[-2][-1] == "]":
                    split[-2] = "\\" + split[-2]
                    reg_paths[i] = {"path" : '/'.join(split[0:len(split)-1]), "pin" : split[-1]}
                else:
                    reg_paths[i] = {"path" : '/'.join(split[0:len(split)-1]), "pin" : split[-1]}

            # For parent hierarchical modules, append all child instance regs
            if self.hierarchical_mode.is_nonleaf_hierarchical():
                with open(os.path.join(os.path.dirname(path), "find_child_modules.json"), "r") as cmf:
                    mod_paths = json.load(cmf)
                for mod_path in mod_paths.items():
                    ilm = next(i for i in self.get_input_ilms() if i.module == mod_path[0])  # type: ILMStruct
                    with open(os.path.join(os.path.dirname(ilm.dir), "find_regs_paths.json"), "r") as crf:
                        child_regs = json.load(crf)
                    for inst_path in mod_path[1]:
                        prefixed_regs = copy.deepcopy(child_regs)
                        for reg in prefixed_regs:
                            reg.update({'path': os.path.join(inst_path, reg['path'])})
                        reg_paths.extend(prefixed_regs)

            f.seek(0) # Move to beginning to rewrite file
            json.dump(reg_paths, f, indent=2) # Elide the truncation because we are always increasing file size
        return True

Other Information

ucli console error:

ucli% source /bwrcq/C/di_wang/intech22/hammer_2025q2/build/FLL/sim-syn-rundir/force_regs.ucli
Error: script /bwrcq/C/di_wang/intech22/hammer_2025q2/build/FLL/sim-syn-rundir/force_regs.ucli stopped at line 6
file /bwrcq/C/di_wang/intech22/hammer_2025q2/build/FLL/sim-syn-rundir/run.tcl, line 12: Error-[UCLI-FORCE-OBJ-NOT-FOUND] Force command error
  Force command on object 'dut_FLL.dut_FD.counter_reg[0]7 .q' failed as the
  object was not found
  Please use 'show -signals|-variables' command to find all valid objects in
  the design hierarchy of interest

force_regs.ucli :

force -deposit {dut_FLL.dut_divider.clk_1g_reg .q} 0
force -deposit {dut_FLL.dut_FD.\counter_reg[0] .q} 0
force -deposit {dut_FLL.dut_FD.\counter_reg[1] .q} 0
force -deposit {dut_FLL.dut_FD.\counter_reg[2] .q} 0
force -deposit {dut_FLL.dut_FD.\counter_reg[3] .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[0]7 .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[1]8 .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[2]9 .q} 0
force -deposit {dut_FLL.dut_FD.\freq_out_reg[0] .q} 0
force -deposit {dut_FLL.dut_FD.\freq_out_reg[1] .q} 0
force -deposit {dut_FLL.dut_FD.\freq_out_reg[2] .q} 0
force -deposit {dut_FLL.dut_FD.\freq_out_reg[3] .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[3]10 .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[0]15 .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[1]16 .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[2]17 .q} 0
force -deposit {dut_FLL.dut_FD.counter_reg[3]18 .q} 0
force -deposit {dut_FLL.dut_FD.freq_out_reg[0]11 .q} 0
force -deposit {dut_FLL.dut_FD.freq_out_reg[1]12 .q} 0
force -deposit {dut_FLL.dut_FD.freq_out_reg[2]13 .q} 0
force -deposit {dut_FLL.dut_FD.freq_out_reg[3]14 .q} 0
force -deposit {dut_FLL.dut_divider.\counter_reg[0] .q} 0
force -deposit {dut_FLL.dut_divider.\counter_reg[1] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[0] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[1] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[2] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[3] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[4] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[5] .q} 0
force -deposit {dut_FLL.dut_DZ_integrator.\fcw_reg[6] .q} 0

find_regs_paths.json:

[
  {
    "path": "dut_divider/clk_1g_reg",
    "pin": "q"
  },
  {
    "path": "dut_divider/\\counter_reg[0]",
    "pin": "q"
  },
  {
    "path": "dut_divider/\\counter_reg[1]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\freq_out_reg[0]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\freq_out_reg[1]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\freq_out_reg[2]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\freq_out_reg[3]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\counter_reg[0]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\counter_reg[1]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\counter_reg[2]",
    "pin": "q"
  },
  {
    "path": "dut_FD/\\counter_reg[3]",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[0]7",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[1]8",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[2]9",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[3]10",
    "pin": "q"
  },
  {
    "path": "dut_FD/freq_out_reg[0]11",
    "pin": "q"
  },
  {
    "path": "dut_FD/freq_out_reg[1]12",
    "pin": "q"
  },
  {
    "path": "dut_FD/freq_out_reg[2]13",
    "pin": "q"
  },
  {
    "path": "dut_FD/freq_out_reg[3]14",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[0]15",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[1]16",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[2]17",
    "pin": "q"
  },
  {
    "path": "dut_FD/counter_reg[3]18",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[0]",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[1]",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[2]",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[3]",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[4]",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[5]",
    "pin": "q"
  },
  {
    "path": "dut_DZ_integrator/\\fcw_reg[6]",
    "pin": "q"
  }
]