@@ -161,7 +161,7 @@ class GemminiTile private (
161161 // regNode := TLFragmenter(4, 4) := TLWidthWidget(8) := TLFragmenter(8, 8) := slaveNode
162162 regNode := tlSlaveXbar.node
163163
164- val scalingFacNode = gemminiParams.scalingFactorMem.map { sfm =>
164+ val scalingFacManager = gemminiParams.scalingFactorMem.map { sfm =>
165165 // since gemmini slave address starts at 0x3000, +0x5000 means
166166 // the scaling factor memory starts 0x8000 + shared mem size,
167167 // which is usually 0x28000 after cluster base address. this address is
@@ -184,10 +184,22 @@ class GemminiTile private (
184184 beatBytes = 8 ,
185185 )))
186186 }
187- scalingFacNode .foreach(_
187+ scalingFacManager .foreach(_
188188 := TLWidthWidget (8 )
189189 := tlSlaveXbar.node)
190190
191+ val scalingFacClient = gemminiParams.scalingFactorMem.map { sfm =>
192+ TLClientNode (Seq (TLMasterPortParameters .v1(
193+ clients = Seq (TLMasterParameters .v2(
194+ name = " gemmini-scaling-fac-client" ,
195+ sourceId = IdRange (0 , 1 << 4 ), // TODO: magic number
196+ emits = TLMasterToSlaveTransferSizes (
197+ putFull = TransferSizes (sfm.bankWidthBytes, sfm.bankWidthBytes)
198+ )
199+ ))
200+ )))
201+ }
202+
191203 val requantizerMuonManager = gemminiParams.requantizer.map { q =>
192204 val gemminiSpadSizeBytes = gemminiParams.gemminiConfig.sp_capacity
193205 .asInstanceOf [CapacityInKilobytes ].kilobytes * 1024
@@ -246,7 +258,7 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
246258 }
247259
248260 // scaling factor
249- outer.scalingFacNode .foreach { scalingFacNode =>
261+ outer.scalingFacManager .foreach { scalingFacNode =>
250262 val conf = outer.gemminiParams.scalingFactorMem.get
251263 val (node, edge) = scalingFacNode.in.head
252264
@@ -278,6 +290,23 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
278290 outer.gemmini.module.mx_io.get.scale_mem_write_act <> scalingFacWriteReqs.last
279291 }
280292
293+ outer.scalingFacClient.foreach { scalingFacNode =>
294+ val (node, edge) = scalingFacNode.out.head
295+ val out = outer.gemmini.module.mx_io.get.scale_factor_out
296+
297+ node.a.bits := edge.Put (
298+ fromSource = 0 .U , // overridden
299+ toAddress = out.bits.addr,
300+ lgSize = log2Ceil(node.params.dataBits / 8 ).U ,
301+ data = out.bits.data,
302+ )._2
303+
304+ val (sourceReady, _) = SourceGenerator (node)
305+ out.ready := node.a.ready && sourceReady
306+ node.a.valid := out.valid && sourceReady
307+ node.d.ready := true .B
308+ }
309+
281310 // requantizer
282311 outer.gemminiParams.requantizer.foreach { q =>
283312 val in = Wire (Decoupled (new RequantizerInBundle (q.numGPUInputLanes, q.inputBits)))
@@ -303,22 +332,13 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
303332
304333 { // output
305334 val (node, edge) = outer.requantizerSmemClient.get.out.head
306- node.a.valid := out.valid
307-
308- // source
309- val sourceGen = Module (new SourceGenerator (q.outputIdBits))
310- sourceGen.io.reclaim.valid := node.d.fire
311- sourceGen.io.reclaim.bits := node.d.bits.source
312- sourceGen.io.gen := node.a.fire
313-
314- out.ready := node.a.ready && sourceGen.io.id.valid
315335
316336 // data
317337 val isFP4 = out.bits.dataType === RequantizerDataType .FP4
318338 val fullWidth = q.numOutputLanes
319339 val halfWidth = q.numOutputLanes / 2
320340 node.a.bits := edge.Put (
321- fromSource = sourceGen.io.id.bits,
341+ fromSource = 0 . U , // gets overridden
322342 toAddress = out.bits.address,
323343 lgSize = Mux (isFP4,
324344 log2Ceil(halfWidth).U , // half byte per lane
@@ -334,6 +354,11 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
334354 )
335355 )._2
336356
357+ // source
358+ val (sourceReady, _) = SourceGenerator (node)
359+ out.ready := node.a.ready && sourceReady
360+ node.a.valid := out.valid && sourceReady
361+ assert(out.fire === node.a.fire)
337362 node.d.ready := true .B
338363 }
339364
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