lsu: load/store depth 4

Author: hansungk

src/main/scala/radiance/muon/LSU.scala

@@ -11,10 +11,10 @@ import org.chipsalliance.cde.config.Field
 case class LoadStoreUnitParams(
     val numLsuLanes: Int = 16, // width of downstream memory interface and writeback; width of execute fixed to # of lanes
 
-    val numGlobalLdqEntries: Int = 16, // limited to 8 decoded global load insts per warp
-    val numGlobalStqEntries: Int = 16, // limited to 4 decoded global store insts per warp
-    val numSharedLdqEntries: Int = 16, // limited to 8 decoded shared load insts per warp
-    val numSharedStqEntries: Int = 16, // limited to 8 decoded shared store insts per warp
+    val numGlobalLdqEntries: Int = 4, // limited to 8 decoded global load insts per warp
+    val numGlobalStqEntries: Int = 4, // limited to 4 decoded global store insts per warp
+    val numSharedLdqEntries: Int = 4, // limited to 8 decoded shared load insts per warp
+    val numSharedStqEntries: Int = 4, // limited to 8 decoded shared store insts per warp
 
     val loadDataEntries: Int = 16, // limited to 16 in-flight / waiting to writeback load requests
     val storeDataEntries: Int = 8, // limited to 8 unissued store requests