Add perfect SW-model LSU config at toplevel

Author: hansungk

chipyard/RadianceConfigs.scala

@@ -238,6 +238,15 @@ class RadianceCyclotronMemConfig extends Config(
   new RadianceBaseConfig
 )
 
+class RadianceCyclotronLSUConfig extends Config(
+  new WithMuonCores(2, location = InCluster(0), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), cyclotronLSU = true, trace = true) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithExtGPUMem() ++
+  new WithRadianceRocket ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
 class RadianceSingleClusterConfig extends Config(
   new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
   new WithMuonCores(2, location = InCluster(0), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), trace = true) ++

src/main/scala/radiance/muon/MuonCore.scala

@@ -48,7 +48,7 @@ case class MuonCoreParams(
   csrAddrBits: Int = 32,
   // memory
   lsu: LoadStoreUnitParams = LoadStoreUnitParams(),
-  lsuUseModel: Boolean = false, // use Cyclotron functional model for LSU
+  lsuUseModel: Boolean = false,  // use Cyclotron functional model for LSU
   logGMEMInFlights: Int = 5,        // per lane
   logCoalGMEMInFlights: Int = 5,    // all lanes
   logNonCoalGMEMInFlights: Int = 5, // all lanes

src/main/scala/radiance/subsystem/Configs.scala

@@ -71,6 +71,7 @@ class WithMuonCores(
   profiler: Boolean,
   cyclotronCore: Boolean,
   cyclotronMem: Boolean,
+  cyclotronLSU: Boolean,
   difftest: Boolean,
   disabled: Boolean,
   numWarps: Option[Int],
@@ -122,13 +123,14 @@ class WithMuonCores(
       // from SIMTCoreParams. TODO: use SIMTCoreParams instead?
       // logSMEMInFlights = log2Ceil(up(SIMTCoreKey).get.numSMEMInFlights),
       lsu = resolvedLsu,
+      lsuUseModel = cyclotronLSU,
       trace = trace || difftest,
       profiler = profiler,
       difftest = difftest,
     )
   }
   case CyclotronLinked => {
-    up(CyclotronLinked) || trace || difftest || cyclotronCore || cyclotronMem || profiler
+    up(CyclotronLinked) || trace || difftest || cyclotronCore || cyclotronMem || cyclotronLSU || profiler
   }
   case TilesLocated(`location`) => {
     if (standalone) {
@@ -172,6 +174,7 @@ class WithMuonCores(
     standalone: Boolean = false, noILP: Boolean = false,
     trace: Boolean = false, profiler: Boolean = true,
     cyclotronCore: Boolean = false, cyclotronMem: Boolean = false,
+    cyclotronLSU: Boolean = false,
     difftest: Boolean = false, disabled: Boolean = false,
     numWarps: Option[Int] = None,
     numLanes: Option[Int] = None,
@@ -186,7 +189,7 @@ class WithMuonCores(
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     },
-    ), standalone, noILP, trace, profiler, cyclotronCore, cyclotronMem,
+    ), standalone, noILP, trace, profiler, cyclotronCore, cyclotronMem, cyclotronLSU,
     difftest, disabled, numWarps, numLanes, numPhysRegs,
     numIssueQueueEntries, lsqDepth, l0i, l0d)
 }