Add performance counter DPI module

Author: hansungk

cyclotron

@@ -412,4 +412,18 @@ void cyclotron_difftest_reg(
   );
 }
 
+void profile_perf_counters_rs(
+    uint64_t inst_retired,
+    uint64_t cycle,
+    uint8_t finished
+);
+
+void profile_perf_counters(
+    uint64_t inst_retired,
+    uint64_t cycle,
+    uint8_t finished
+) {
+  profile_perf_counters_rs(inst_retired, cycle, finished);
+}
+
 } // extern "C"

src/main/resources/csrc/Cyclotron.cc

@@ -0,0 +1,32 @@
+module ProfilerBlackBox #(
+  parameter COUNTER_WIDTH = 64
+) (
+  input clock,
+  input reset,
+  input logic                     finished,
+  input logic [COUNTER_WIDTH-1:0] perf_backend_execute_instRetired,
+  input logic [COUNTER_WIDTH-1:0] perf_backend_execute_cycle
+);
+
+  `include "Cyclotron.vh"
+
+  import "DPI-C" function void profile_perf_counters(
+    input longint inst_retired,
+    input longint cycle,
+    input bit     finished
+  );
+
+  initial cyclotron_init_task();
+
+  always @(posedge clock) begin
+    if (reset) begin
+    end else begin
+      profile_perf_counters(
+        perf_backend_execute_instRetired,
+        perf_backend_execute_cycle,
+        finished
+      );
+    end
+  end
+
+endmodule

src/main/resources/vsrc/Profiler.v

@@ -17,7 +17,7 @@ class Execute(implicit p: Parameters) extends CoreModule()(p) {
     val feCSR = Flipped(feCSRIO)
     val barrier = barrierIO
     val softReset = Input(Bool())
-    val perf = Output(new ExecutePerfIO)
+    val perf = new ExecutePerfIO
   })
 
   val aluPipe = Module(new ALUPipe())
@@ -81,7 +81,7 @@ class Execute(implicit p: Parameters) extends CoreModule()(p) {
 }
 
 class ExecutePerfIO(implicit p: Parameters) extends CoreBundle()(p) {
-  val instRetired = UInt(Perf.counterWidth.W)
-  val cycle =  UInt(Perf.counterWidth.W)
+  val instRetired = Output(UInt(Perf.counterWidth.W))
+  val cycle =  Output(UInt(Perf.counterWidth.W))
   // TODO: issue valid, execute fire
 }

src/main/scala/radiance/muon/Execute.scala

@@ -231,6 +231,11 @@ class MuonCoreTop(implicit p: Parameters) extends LazyModule with HasCoreParamet
     core.io.coreId := 0.U
     core.io.clusterId := 0.U
 
+    // performance counters
+    val cperf = Module(new Profiler)
+    cperf.io.perf <> core.io.perf
+    cperf.io.finished := core.io.finished
+
     // RTL/model diff-test
     if (core.test) {
       val cdiff = Module(new CyclotronDiffTest(tick = true))
@@ -1092,40 +1097,70 @@ class CyclotronDiffTest(tick: Boolean = true)
     boxtr.address := tr.address
     boxtr.data := tr.data.asUInt
   }
-}
 
-class CyclotronDiffTestBlackBox(tick: Boolean)(implicit val p: Parameters)
-extends BlackBox(Map(
-      "ARCH_LEN"     -> p(MuonKey).archLen,
-      "INST_BITS"    -> p(MuonKey).instBits,
-      "NUM_WARPS"    -> p(MuonKey).numWarps,
-      "NUM_LANES"    -> p(MuonKey).numLanes,
-      "OP_BITS"      -> Isa.opcodeBits,
-      "REG_BITS"     -> Isa.regBits,
-      "IMM_BITS"     -> 32,
-      "CSR_IMM_BITS" -> Isa.csrImmBits,
-      "PRED_BITS"    -> Isa.predBits,
-      "SIM_TICK"     -> (if (tick) 1 else 0),
-)) with HasBlackBoxResource with HasCoreParameters {
-  val io = IO(new Bundle {
-    val clock = Input(Clock())
-    val reset = Input(Bool())
+  class CyclotronDiffTestBlackBox(tick: Boolean)(implicit val p: Parameters)
+  extends BlackBox(Map(
+        "ARCH_LEN"     -> p(MuonKey).archLen,
+        "INST_BITS"    -> p(MuonKey).instBits,
+        "NUM_WARPS"    -> p(MuonKey).numWarps,
+        "NUM_LANES"    -> p(MuonKey).numLanes,
+        "OP_BITS"      -> Isa.opcodeBits,
+        "REG_BITS"     -> Isa.regBits,
+        "IMM_BITS"     -> 32,
+        "CSR_IMM_BITS" -> Isa.csrImmBits,
+        "PRED_BITS"    -> Isa.predBits,
+        "SIM_TICK"     -> (if (tick) 1 else 0),
+  )) with HasBlackBoxResource with HasCoreParameters {
+    val io = IO(new Bundle {
+      val clock = Input(Clock())
+      val reset = Input(Bool())
 
-    val trace = Input(new Bundle {
-      val valid = Bool()
-      val pc = pcT
-      val warpId = widT
-      val regs = Vec(Isa.maxNumRegs, new Bundle {
-        val enable = Bool()
-        val address = pRegT
-        val data = UInt((muonParams.numLanes * muonParams.archLen).W)
+      val trace = Input(new Bundle {
+        val valid = Bool()
+        val pc = pcT
+        val warpId = widT
+        val regs = Vec(Isa.maxNumRegs, new Bundle {
+          val enable = Bool()
+          val address = pRegT
+          val data = UInt((muonParams.numLanes * muonParams.archLen).W)
+        })
       })
     })
+
+    addResource("/vsrc/CyclotronDiffTest.v")
+    addResource("/vsrc/Cyclotron.vh")
+    addResource("/csrc/Cyclotron.cc")
+  }
+}
+
+class Profiler(implicit p: Parameters) extends CoreModule {
+  val io = IO(new Bundle {
+    val finished = Input(Bool())
+    val perf = Flipped(new PerfIO)
   })
 
-  addResource("/vsrc/CyclotronDiffTest.v")
-  addResource("/vsrc/Cyclotron.vh")
-  addResource("/csrc/Cyclotron.cc")
+  val bbox = Module(new ProfilerBlackBox()(p))
+  bbox.io.clock := clock
+  bbox.io.reset := reset.asBool
+
+  bbox.io.perf <> io.perf
+  bbox.io.finished := io.finished
+
+  class ProfilerBlackBox()(implicit val p: Parameters)
+  extends BlackBox(Map(
+        "COUNTER_WIDTH" -> Perf.counterWidth,
+  )) with HasBlackBoxResource with HasCoreParameters {
+    val io = IO(new Bundle {
+      val clock = Input(Clock())
+      val reset = Input(Bool())
+      val finished = Input(Bool())
+      val perf = Flipped(new PerfIO)
+    })
+
+    addResource("/vsrc/Profiler.v")
+    addResource("/vsrc/Cyclotron.vh")
+    addResource("/csrc/Cyclotron.cc")
+  }
 }
 
 class CyclotronMemBlackBox(implicit p: Parameters) extends CyclotronBlackBox