Parameterize numLanes at top config

adjust l0d line size to be min(64B, warpLen * wordSize) so that the
current assumption of l0d being fragmented into the narrower l1 lines
hold.

Author: hansungk

chipyard/RadianceConfigs.scala

@@ -264,6 +264,45 @@ class RadianceSingleClusterIssueDepth8Config extends RadianceSingleClusterIssueD
 class RadianceSingleClusterIssueDepth16Config extends RadianceSingleClusterIssueDepthConfig(16)
 class RadianceSingleClusterIssueDepth32Config extends RadianceSingleClusterIssueDepthConfig(32)
 
+object RadianceWarpLenConfig {
+  private val minL0dLineBytes = 64
+  private val wordBytes = 32 / 8
+  private def warpBytes(warpLen: Int): Int = warpLen * wordBytes
+  private def withBlockBytes(cache: DCacheParams, blockBytes: Int): DCacheParams =
+    cache.copy(rowBits = blockBytes * 8, blockBytes = blockBytes)
+
+  def l0i(warpLen: Int): DCacheParams =
+    L0iCacheConfig
+  def l0d(warpLen: Int): DCacheParams =
+    withBlockBytes(L0dCacheConfig, minL0dLineBytes max warpBytes(warpLen))
+  def l1(warpLen: Int): DCacheParams =
+    L1CacheConfig
+}
+
+class RadianceSingleClusterWarpLenConfig(warpLen: Int) extends Config(
+  new WithMuonCores(
+    2,
+    location = InCluster(0),
+    noILP = false,
+    l0i = Some(RadianceWarpLenConfig.l0i(warpLen)),
+    l0d = Some(RadianceWarpLenConfig.l0d(warpLen)),
+    trace = true,
+    numLanes = Some(warpLen)
+  ) ++
+  new WithSIMTConfig(numWarps = 8, numLanes = warpLen, numLsuLanes = warpLen, numSMEMInFlights = 8) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = RadianceWarpLenConfig.l1(warpLen)) ++
+  new WithExtGPUMem() ++
+  new WithRadianceRocket ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
+class RadianceSingleClusterWarpLen4Config extends RadianceSingleClusterWarpLenConfig(4)
+class RadianceSingleClusterWarpLen8Config extends RadianceSingleClusterWarpLenConfig(8)
+class RadianceSingleClusterWarpLen16Config extends RadianceSingleClusterWarpLenConfig(16)
+class RadianceSingleClusterWarpLen32Config extends RadianceSingleClusterWarpLenConfig(32)
+class RadianceSingleClusterWarpLen64Config extends RadianceSingleClusterWarpLenConfig(64)
+
 class RadianceSingleClusterLargeICacheConfig extends Config(
   new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
   new WithMuonCores(2, location = InCluster(0), noILP = false, l0i = Some(L0iCacheHugeConfig), l0d = Some(L0dCacheConfig), trace = true) ++

cyclotron

@@ -42,7 +42,7 @@ case class MuonTileParams(
     if (sourceIds == 0) 0 else 1 << log2Ceil(sourceIds)
 
   def l1ReqTagBits: Int = {
-    val coalescedReqWidth = core.numLanes * core.archLen / 8
+    val coalescedReqWidth = dcache.map(_.blockBytes).getOrElse(core.numLanes * core.archLen / 8)
     require(coalescedReqWidth >= l1CacheLineBytes)
     require(coalescedReqWidth % l1CacheLineBytes == 0)
     require(isPow2(coalescedReqWidth / l1CacheLineBytes))
@@ -259,10 +259,12 @@ class MuonTile(
   })
 
 
-  val coalescedReqWidth = muonParams.core.numLanes * muonParams.core.archLen / 8
+  val warpBytes = muonParams.core.numLanes * muonParams.core.archLen / 8
+  val coalescedReqWidth = muonParams.dcache.map(_.blockBytes).getOrElse(warpBytes)
 
   val (l0dOut, l0dIn, l0dFlushRegNode) = muonParams.dcache.map { l0dParams =>
-    require(muonParams.dcache.map(_.blockBytes).getOrElse(coalescedReqWidth) == coalescedReqWidth)
+    require(l0dParams.blockBytes == coalescedReqWidth)
+    require(l0dParams.blockBytes >= warpBytes)
     println(f"l0d flush address is ${muonParams.peripheralAddr}%x")
     val l0d = LazyModule(new TLULNBDCache(TLNBDCacheParams(
       id = tileId,

src/main/scala/radiance/muon/MuonTile.scala

@@ -18,6 +18,8 @@ import testchipip.soc.SubsystemInjectorKey
 import radiance.cluster._
 import radiance.memory._
 import radiance.muon._
+import radiance.muon.backend.fp.FPPipeParams
+import radiance.muon.backend.int.IntPipeParams
 import radiance.virgo.{NumVortexCores, VirgoClusterParams, VortexCoreParams, VortexL1Key}
 import radiance.muon.LoadStoreUnitParams
 import radiance.unittest.CyclotronLinked
@@ -71,6 +73,7 @@ class WithMuonCores(
   cyclotron: Boolean,
   difftest: Boolean,
   disabled: Boolean,
+  numLanes: Option[Int],
   numIssueQueueEntries: Int,
   l0i: Option[DCacheParams],
   l0d: Option[DCacheParams],
@@ -81,18 +84,32 @@ class WithMuonCores(
       assert(up(RadianceSimArgs),
              "WithMuonCores: difftest cannot be enabled in non-sim mode!")
     }
+    val simt = up(SIMTCoreKey).get
+    val resolvedNumLanes = numLanes.getOrElse(simt.numLanes)
+    val intPipe = numLanes.map { lanes =>
+      IntPipeParams(numALULanes = lanes, numMulDivLanes = lanes)
+    }
+    val fpPipe = numLanes.map { lanes =>
+      FPPipeParams(
+        numFP32Lanes = (lanes / 2).max(1),
+        numFP32DivLanes = (lanes / 8).max(1),
+        numFP16ExpLanes = (lanes / 4).max(1)
+      )
+    }
     MuonCoreParams(
-      numWarps = up(SIMTCoreKey).get.numWarps,
-      numLanes = up(SIMTCoreKey).get.numLanes,
+      numWarps = simt.numWarps,
+      numLanes = resolvedNumLanes,
       numCores = n,
       numClusters = 2, // TODO: magic number
       noILP = noILP,
       numIssueQueueEntries = numIssueQueueEntries,
+      intPipe = intPipe.getOrElse(MuonCoreParams().intPipe),
+      fpPipe = fpPipe.getOrElse(MuonCoreParams().fpPipe),
       // for muon, numSMEMInFlights controlled by lsu parameters, rather than 
       // from SIMTCoreParams. TODO: use SIMTCoreParams instead?
       // logSMEMInFlights = log2Ceil(up(SIMTCoreKey).get.numSMEMInFlights),
       lsu = LoadStoreUnitParams(
-        numLsuLanes = up(SIMTCoreKey).get.numLsuLanes
+        numLsuLanes = numLanes.getOrElse(simt.numLsuLanes)
       ),
       trace = trace || difftest,
       difftest = difftest,
@@ -142,6 +159,7 @@ class WithMuonCores(
     standalone: Boolean = false, noILP: Boolean = false,
     trace: Boolean = false, cyclotron: Boolean = false,
     difftest: Boolean = false, disabled: Boolean = false,
+    numLanes: Option[Int] = None,
     numIssueQueueEntries: Int = 8,
     l0i: Option[DCacheParams] = None, l0d: Option[DCacheParams] = None)
   = this(n, location, RocketCrossingParams(
@@ -151,7 +169,7 @@ class WithMuonCores(
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     },
-  ), standalone, noILP, trace, cyclotron, difftest, disabled, numIssueQueueEntries, l0i, l0d)
+  ), standalone, noILP, trace, cyclotron, difftest, disabled, numLanes, numIssueQueueEntries, l0i, l0d)
 }
 
 class WithCyclotronCores(