Parameterize register file size to toplevel configs

scale architectural regs by physregs / 2, but cap to maximum 128 to be
congruent with compiler codegen.

Author: hansungk

chipyard/RadianceConfigs.scala

@@ -240,7 +240,6 @@ class RadianceSingleClusterConfig extends Config(
 )
 
 class RadianceSingleClusterIssueDepthConfig(issueQueueEntries: Int) extends Config(
-  new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
   new WithMuonCores(
     2,
     location = InCluster(0),
@@ -310,7 +309,10 @@ class RadianceSingleClusterWarpDepthConfig(warpDepth: Int) extends Config(
     noILP = false,
     l0i = Some(L0iCacheConfig),
     l0d = Some(L0dCacheConfig),
+    trace = false,
     profiler = false,
+    cyclotron = false,
+    difftest = false,
     numWarps = Some(warpDepth)
   ) ++
   new WithSIMTConfig(numWarps = warpDepth, numLanes = 16, numLsuLanes = 16, numSMEMInFlights = 8) ++
@@ -327,6 +329,32 @@ class RadianceSingleClusterWarpDepth8Config extends RadianceSingleClusterWarpDep
 class RadianceSingleClusterWarpDepth16Config extends RadianceSingleClusterWarpDepthConfig(16)
 class RadianceSingleClusterWarpDepth32Config extends RadianceSingleClusterWarpDepthConfig(32)
 
+class RadianceSingleClusterPhysRegConfig(numPhysRegs: Int) extends Config(
+  new WithMuonCores(
+    2,
+    location = InCluster(0),
+    noILP = false,
+    l0i = Some(L0iCacheConfig),
+    l0d = Some(L0dCacheConfig),
+    trace = false,
+    profiler = false,
+    cyclotron = false,
+    difftest = false,
+    numPhysRegs = Some(numPhysRegs)
+  ) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithExtGPUMem() ++
+  new WithRadianceRocket ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
+class RadianceSingleClusterPhysReg64Config extends RadianceSingleClusterPhysRegConfig(64)
+class RadianceSingleClusterPhysReg128Config extends RadianceSingleClusterPhysRegConfig(128)
+class RadianceSingleClusterPhysReg256Config extends RadianceSingleClusterPhysRegConfig(256)
+class RadianceSingleClusterPhysReg512Config extends RadianceSingleClusterPhysRegConfig(512)
+class RadianceSingleClusterPhysReg1024Config extends RadianceSingleClusterPhysRegConfig(1024)
+
 class RadianceSingleClusterLargeICacheConfig extends Config(
   new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
   new WithMuonCores(2, location = InCluster(0), noILP = false, l0i = Some(L0iCacheHugeConfig), l0d = Some(L0dCacheConfig), trace = true) ++

src/main/scala/radiance/subsystem/Configs.scala

@@ -76,6 +76,7 @@ class WithMuonCores(
   disabled: Boolean,
   numWarps: Option[Int],
   numLanes: Option[Int],
+  numPhysRegs: Option[Int],
   numIssueQueueEntries: Int,
   l0i: Option[DCacheParams],
   l0d: Option[DCacheParams],
@@ -89,6 +90,7 @@ class WithMuonCores(
     val simt = up(SIMTCoreKey).get
     val resolvedNumWarps = numWarps.getOrElse(simt.numWarps)
     val resolvedNumLanes = numLanes.getOrElse(simt.numLanes)
+    val resolvedNumPhysRegs = numPhysRegs.getOrElse(MuonCoreParams().numPhysRegs)
     val intPipe = numLanes.map { lanes =>
       IntPipeParams(numALULanes = lanes, numMulDivLanes = lanes)
     }
@@ -102,6 +104,8 @@ class WithMuonCores(
     MuonCoreParams(
       numWarps = resolvedNumWarps,
       numLanes = resolvedNumLanes,
+      numPhysRegs = resolvedNumPhysRegs,
+      numArchRegs = (resolvedNumPhysRegs / 2).min(128),
       numCores = n,
       numClusters = 2, // TODO: magic number
       noILP = noILP,
@@ -165,6 +169,7 @@ class WithMuonCores(
     difftest: Boolean = false, disabled: Boolean = false,
     numWarps: Option[Int] = None,
     numLanes: Option[Int] = None,
+    numPhysRegs: Option[Int] = None,
     numIssueQueueEntries: Int = 8,
     l0i: Option[DCacheParams] = None, l0d: Option[DCacheParams] = None)
   = this(n, location, RocketCrossingParams(
@@ -174,7 +179,7 @@ class WithMuonCores(
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     },
-  ), standalone, noILP, trace, profiler, cyclotron, difftest, disabled, numWarps, numLanes, numIssueQueueEntries, l0i, l0d)
+  ), standalone, noILP, trace, profiler, cyclotron, difftest, disabled, numWarps, numLanes, numPhysRegs, numIssueQueueEntries, l0i, l0d)
 }
 
 class WithCyclotronCores(