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Separate parameter to enable cyclotron profiler
1 parent 23669c8 commit 49fccfc

5 files changed

Lines changed: 19 additions & 14 deletions

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chipyard/RadianceConfigs.scala

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -247,6 +247,7 @@ class RadianceSingleClusterIssueDepthConfig(issueQueueEntries: Int) extends Conf
247247
noILP = false,
248248
l0i = Some(L0iCacheConfig),
249249
l0d = Some(L0dCacheConfig),
250+
profiler = false,
250251
numIssueQueueEntries = issueQueueEntries
251252
) ++
252253
new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
@@ -285,6 +286,7 @@ class RadianceSingleClusterWarpLenConfig(warpLen: Int) extends Config(
285286
noILP = false,
286287
l0i = Some(RadianceWarpLenConfig.l0i(warpLen)),
287288
l0d = Some(RadianceWarpLenConfig.l0d(warpLen)),
289+
profiler = false,
288290
numLanes = Some(warpLen)
289291
) ++
290292
new WithSIMTConfig(numWarps = 8, numLanes = warpLen, numLsuLanes = warpLen, numSMEMInFlights = 8) ++

src/main/scala/radiance/muon/MuonCore.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ case class MuonCoreParams(
5555
barrierBits: Int = 4,
5656
debug: Boolean = false, // enable extra IOs for debug (ex: PC)
5757
trace: Boolean = false, // enable instruction trace generation
58+
profiler: Boolean = true, // enable performance profiling report generation
5859
difftest: Boolean = false // enable arch-state differential testing
5960
// against cyclotron
6061
) extends PhysicalCoreParams {

src/main/scala/radiance/muon/MuonTile.scala

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -419,8 +419,7 @@ class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
419419
}
420420

421421
// performance counters
422-
val isSim = p(RadianceSimArgs)
423-
if (isSim) {
422+
if (core.muonParams.profiler) {
424423
val cperf = Module(new Profiler(
425424
clusterId = outer.muonParams.clusterId,
426425
coreId = outer.muonParams.coreId,
@@ -431,7 +430,6 @@ class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
431430

432431
// RTL-model difftest
433432
if (core.muonParams.difftest) {
434-
assert(isSim, "muon traces cannot enabled in non-sim mode!")
435433
val cdiff = Module(new CyclotronDiffTest(
436434
clusterId = outer.muonParams.clusterId,
437435
coreId = outer.muonParams.coreId,

src/main/scala/radiance/subsystem/Configs.scala

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@ class WithMuonCores(
6969
standalone: Boolean,
7070
noILP: Boolean,
7171
trace: Boolean,
72+
profiler: Boolean,
7273
/** cyclotron-as-a-tile: use golden core model */
7374
cyclotron: Boolean,
7475
difftest: Boolean,
@@ -80,9 +81,9 @@ class WithMuonCores(
8081
) extends Config((site, here, up) => {
8182
// for use in tile-less standalone instantiation
8283
case MuonKey => {
83-
if (difftest) {
84+
if (difftest || trace || profiler) {
8485
assert(up(RadianceSimArgs),
85-
"WithMuonCores: difftest cannot be enabled in non-sim mode!")
86+
"cyclotron features cannot be enabled in non-sim mode!")
8687
}
8788
val simt = up(SIMTCoreKey).get
8889
val resolvedNumLanes = numLanes.getOrElse(simt.numLanes)
@@ -112,11 +113,12 @@ class WithMuonCores(
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numLsuLanes = numLanes.getOrElse(simt.numLsuLanes)
113114
),
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trace = trace || difftest,
116+
profiler = profiler,
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difftest = difftest,
116118
)
117119
}
118120
case CyclotronLinked => {
119-
up(CyclotronLinked) || site(RadianceSimArgs) || trace || difftest || cyclotron
121+
up(CyclotronLinked) || trace || difftest || cyclotron || profiler
120122
}
121123
case TilesLocated(`location`) => {
122124
if (standalone) {
@@ -157,7 +159,7 @@ class WithMuonCores(
157159
// constructor override that omits `crossing`
158160
def this(n: Int, location: HierarchicalLocation = InSubsystem,
159161
standalone: Boolean = false, noILP: Boolean = false,
160-
trace: Boolean = false, cyclotron: Boolean = false,
162+
trace: Boolean = false, profiler: Boolean = true, cyclotron: Boolean = false,
161163
difftest: Boolean = false, disabled: Boolean = false,
162164
numLanes: Option[Int] = None,
163165
numIssueQueueEntries: Int = 8,
@@ -169,7 +171,7 @@ class WithMuonCores(
169171
case InSubsystem => CBUS
170172
case InCluster(clusterId) => CCBUS(clusterId)
171173
},
172-
), standalone, noILP, trace, cyclotron, difftest, disabled, numLanes, numIssueQueueEntries, l0i, l0d)
174+
), standalone, noILP, trace, profiler, cyclotron, difftest, disabled, numLanes, numIssueQueueEntries, l0i, l0d)
173175
}
174176

175177
class WithCyclotronCores(

src/main/scala/radiance/unittest/Muon.scala

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -234,12 +234,14 @@ class MuonCoreTop(implicit p: Parameters) extends LazyModule with HasCoreParamet
234234
}
235235

236236
// performance counters
237-
val cperf = Module(new Profiler (
238-
clusterId = 0,
239-
coreId = 0,
240-
))
241-
cperf.io.perf <> core.io.perf
242-
cperf.io.finished := core.io.finished
237+
if (core.muonParams.profiler) {
238+
val cperf = Module(new Profiler (
239+
clusterId = 0,
240+
coreId = 0,
241+
))
242+
cperf.io.perf <> core.io.perf
243+
cperf.io.finished := core.io.finished
244+
}
243245

244246
// RTL-model difftest
245247
if (core.muonParams.difftest) {

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