@@ -69,6 +69,7 @@ class WithMuonCores(
6969 standalone : Boolean ,
7070 noILP : Boolean ,
7171 trace : Boolean ,
72+ profiler : Boolean ,
7273 /** cyclotron-as-a-tile: use golden core model */
7374 cyclotron : Boolean ,
7475 difftest : Boolean ,
@@ -80,9 +81,9 @@ class WithMuonCores(
8081) extends Config ((site, here, up) => {
8182 // for use in tile-less standalone instantiation
8283 case MuonKey => {
83- if (difftest) {
84+ if (difftest || trace || profiler ) {
8485 assert(up(RadianceSimArgs ),
85- " WithMuonCores: difftest cannot be enabled in non-sim mode!" )
86+ " cyclotron features cannot be enabled in non-sim mode!" )
8687 }
8788 val simt = up(SIMTCoreKey ).get
8889 val resolvedNumLanes = numLanes.getOrElse(simt.numLanes)
@@ -112,11 +113,12 @@ class WithMuonCores(
112113 numLsuLanes = numLanes.getOrElse(simt.numLsuLanes)
113114 ),
114115 trace = trace || difftest,
116+ profiler = profiler,
115117 difftest = difftest,
116118 )
117119 }
118120 case CyclotronLinked => {
119- up(CyclotronLinked ) || site( RadianceSimArgs ) || trace || difftest || cyclotron
121+ up(CyclotronLinked ) || trace || difftest || cyclotron || profiler
120122 }
121123 case TilesLocated (`location`) => {
122124 if (standalone) {
@@ -157,7 +159,7 @@ class WithMuonCores(
157159 // constructor override that omits `crossing`
158160 def this (n : Int , location : HierarchicalLocation = InSubsystem ,
159161 standalone : Boolean = false , noILP : Boolean = false ,
160- trace : Boolean = false , cyclotron : Boolean = false ,
162+ trace : Boolean = false , profiler : Boolean = true , cyclotron : Boolean = false ,
161163 difftest : Boolean = false , disabled : Boolean = false ,
162164 numLanes : Option [Int ] = None ,
163165 numIssueQueueEntries : Int = 8 ,
@@ -169,7 +171,7 @@ class WithMuonCores(
169171 case InSubsystem => CBUS
170172 case InCluster (clusterId) => CCBUS (clusterId)
171173 },
172- ), standalone, noILP, trace, cyclotron, difftest, disabled, numLanes, numIssueQueueEntries, l0i, l0d)
174+ ), standalone, noILP, trace, profiler, cyclotron, difftest, disabled, numLanes, numIssueQueueEntries, l0i, l0d)
173175}
174176
175177class WithCyclotronCores (
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