Merge branch 'main' of https://github.com/ucb-bar/radiance

Author: richardyrh

chipyard/RadianceConfigs.scala

@@ -144,10 +144,20 @@ class RadianceBringupHostConfig extends Config(
   new chipyard.NoCoresConfig)
 
 class RadianceMuonConfig extends Config(
-  new WithMuonCores(1, difftest = true, location = InCluster(0), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig)) ++
+  new WithMuonCores(1, location = InCluster(0), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), difftest = true) ++
   new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
   new WithExtGPUMem() ++
   new freechips.rocketchip.rocket.WithCFlushEnabled ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
+class RadianceCyclotronConfig extends Config(
+  new WithMuonCores(1, location = InCluster(0), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), cyclotron = true) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithExtGPUMem() ++
+  new freechips.rocketchip.rocket.WithCFlushEnabled ++
+  new WithGPUResetAggregator(defaultReset = false) ++
   new RadianceBaseConfig
 )
 

cyclotron

@@ -246,6 +246,16 @@ is set for lanes with zero `rs1` values.  Nothing is written back to `rd`.
 * If no lanes have a non-zero `rs1` value (zero for `vx_pred_n`), set tmask
 to the value of `rs2` of the "leader" lane, i.e. the left-most active lane.
 
+#### `vx_wspawn`
+
+```
+vx_spawn rs1, rs2
+```
+
+Activates warps 1 up to the value of `rs1` in the "leader" lane, if not already active. Has no effect on warp 0.
+Sets `PC` of newly active warps to the value of `rs2` in the "leader" lane. Sets tmask of newly active warps to all 1's.  
+
+Note: this will eventually be superceded by command processor + neutrino
 
 ## New Registers
 

docs/isa.md

@@ -171,7 +171,29 @@ void cyclotron_frontend(
     );
 }
 
-void cyclotron_tile_tick_rs();
+void cyclotron_tile_tick_rs(
+    uint8_t*  imem_req_valid_ptr,
+    uint8_t   imem_req_ready,
+    uint32_t* imem_req_bits_address_ptr,
+    uint64_t* imem_req_bits_tag_ptr,
+    uint8_t*  imem_resp_ready_ptr,
+    uint8_t   imem_resp_valid,
+    uint64_t  imem_resp_bits_tag,
+    uint64_t  imem_resp_bits_data,
+    uint8_t*  dmem_req_valid_vec,
+    const uint8_t* dmem_req_ready_vec,
+    uint8_t*  dmem_req_bits_store_vec,
+    uint32_t* dmem_req_bits_address_vec,
+    uint8_t*  dmem_req_bits_size_vec,
+    uint32_t* dmem_req_bits_tag_vec,
+    uint32_t* dmem_req_bits_data_vec,
+    uint8_t*  dmem_req_bits_mask_vec,
+    uint8_t*  dmem_resp_ready_vec,
+    const uint8_t* dmem_resp_valid_vec,
+    const uint32_t* dmem_resp_bits_tag_vec,
+    const uint32_t* dmem_resp_bits_data_vec,
+    uint8_t*  finished_ptr
+);
 
 void cyclotron_tile_tick(
     uint8_t*  imem_req_valid_ptr,
@@ -196,28 +218,29 @@ void cyclotron_tile_tick(
     const uint32_t* dmem_resp_bits_data_vec,
     uint8_t*  finished_ptr
 ) {
-    (void)imem_req_valid_ptr;
-    (void)imem_req_ready;
-    (void)imem_req_bits_address_ptr;
-    (void)imem_req_bits_tag_ptr;
-    (void)imem_resp_ready_ptr;
-    (void)imem_resp_valid;
-    (void)imem_resp_bits_tag;
-    (void)imem_resp_bits_data;
-    (void)dmem_req_valid_vec;
-    (void)dmem_req_ready_vec;
-    (void)dmem_req_bits_store_vec;
-    (void)dmem_req_bits_address_vec;
-    (void)dmem_req_bits_size_vec;
-    (void)dmem_req_bits_tag_vec;
-    (void)dmem_req_bits_data_vec;
-    (void)dmem_req_bits_mask_vec;
-    (void)dmem_resp_ready_vec;
-    (void)dmem_resp_valid_vec;
-    (void)dmem_resp_bits_tag_vec;
-    (void)dmem_resp_bits_data_vec;
-    (void)finished_ptr;
-    cyclotron_tile_tick_rs();
+    cyclotron_tile_tick_rs(
+        imem_req_valid_ptr,
+        imem_req_ready,
+        imem_req_bits_address_ptr,
+        imem_req_bits_tag_ptr,
+        imem_resp_ready_ptr,
+        imem_resp_valid,
+        imem_resp_bits_tag,
+        imem_resp_bits_data,
+        dmem_req_valid_vec,
+        dmem_req_ready_vec,
+        dmem_req_bits_store_vec,
+        dmem_req_bits_address_vec,
+        dmem_req_bits_size_vec,
+        dmem_req_bits_tag_vec,
+        dmem_req_bits_data_vec,
+        dmem_req_bits_mask_vec,
+        dmem_resp_ready_vec,
+        dmem_resp_valid_vec,
+        dmem_resp_bits_tag_vec,
+        dmem_resp_bits_data_vec,
+        finished_ptr
+    );
 }
 
 void cyclotron_backend_rs(

src/main/resources/csrc/Cyclotron.cc

@@ -1,22 +1,12 @@
-module CyclotronTile #(
+module CyclotronTileBlackBox #(
   parameter ARCH_LEN = 32,
   parameter INST_BITS = 64,
   parameter IMEM_TAG_BITS = 32,
   parameter DMEM_DATA_BITS = 32,
   parameter DMEM_TAG_BITS = 32,
-  parameter NUM_WARPS = 8,
   parameter NUM_LANES = 16,
-  parameter OP_BITS = 9,
-  parameter REG_BITS = 8,
-  parameter IMM_BITS = 32,
-  parameter CSR_IMM_BITS = 8,
-  parameter PRED_BITS = 4,
   localparam DMEM_SIZE_BITS = $clog2($clog2(DMEM_DATA_BITS / 8) + 1),
-  localparam DMEM_MASK_BITS = (DMEM_DATA_BITS / 8),
-  localparam OPNOEXT_BITS = 7,
-  localparam OPEXT_BITS = 2,
-  localparam WARP_ID_BITS = $clog2(NUM_WARPS),
-  localparam WARP_COUNT_BITS = $clog2(NUM_WARPS+1)
+  localparam DMEM_MASK_BITS = (DMEM_DATA_BITS / 8)
 ) (
   input clock,
   input reset,
@@ -42,6 +32,7 @@ module CyclotronTile #(
   input  logic [NUM_LANES-1:0]                  dmem_resp_valid,
   input  logic [(NUM_LANES*DMEM_TAG_BITS)-1:0]  dmem_resp_bits_tag,
   input  logic [(NUM_LANES*DMEM_DATA_BITS)-1:0] dmem_resp_bits_data,
+
   output logic finished
 );
   `include "Cyclotron.vh"

src/main/resources/vsrc/CyclotronTile.v

@@ -15,7 +15,7 @@ import org.chipsalliance.diplomacy.lazymodule.LazyModule
 import radiance.cluster.{CacheFlushNode, SoftResetFinishNode}
 import radiance.memory._
 import radiance.subsystem._
-import radiance.unittest.{CyclotronDiffTest, Profiler}
+import radiance.unittest.{CyclotronTile, CyclotronDiffTest, Profiler}
 
 case class MuonTileParams(
   core: MuonCoreParams = MuonCoreParams(),
@@ -26,6 +26,7 @@ case class MuonTileParams(
   icacheUsingD: Option[DCacheParams] = None,
   dcache: Option[DCacheParams] = None,
   peripheralAddr: BigInt = 0,
+  cyclotron: Boolean = false,
   disabled: Boolean = false,
   btb: Option[BTBParams] = None,
   beuAddr: Option[BigInt] = None,
@@ -327,8 +328,11 @@ class MuonTile(
     Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
   }
 
-//  val muon = Module(new Muon()(newP))
-  override lazy val module = new MuonTileModuleImp(this)
+  override lazy val module = if (muonParams.cyclotron) {
+    new CyclotronTileModuleImp(this)
+  } else {
+    new MuonTileModuleImp(this)
+  }
 
   override def makeMasterBoundaryBuffers(
       crossing: ClockCrossingType
@@ -357,13 +361,14 @@ class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
   muon.io.coreId := outer.muonParams.coreId.U
   muon.io.clusterId := outer.muonParams.clusterId.U
 
-  muon.io.softReset := outer.softResetFinishSlave.in.head._1.softReset
+  val softReset = outer.softResetFinishSlave.in.head._1.softReset
+  muon.io.softReset := softReset
   outer.softResetFinishSlave.in.head._1.finished := muon.io.finished
 
   outer.reportCease(None)
   outer.reportWFI(None)
 
-  when (outer.muonParams.disabled.B || muon.io.softReset) {
+  when (outer.muonParams.disabled.B || softReset) {
     muon.io.imem.req.ready := false.B
     muon.io.imem.resp.valid := false.B // responses will be dropped
     outer.icacheWordNode.out.foreach(_._1.a.valid := false.B)
@@ -386,3 +391,42 @@ class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
     cdiff.io.trace <> muon.io.trace.get
   }
 }
+
+class CyclotronTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
+  val cyclotron = Module(new CyclotronTile)
+
+  MuonMemTL.connectTL(cyclotron.io.imem.req, cyclotron.io.imem.resp, outer.icacheWordNode)
+
+  MuonMemTL.multiConnectTL(cyclotron.io.dmem.req, cyclotron.io.dmem.resp, outer.innerLsuNodes)
+  // TODO: smem
+  // MuonMemTL.multiConnectTL(cyclotron.io.smem.req, cyclotron.io.smem.resp, outer.innerSmemNodes)
+
+  // TODO: barrier
+  // val (barrier, _) = outer.barrierMaster.out.head
+  // barrier.req <> cyclotron.io.barrier.req
+  // barrier.resp <> cyclotron.io.barrier.resp
+
+  // TODO: flush
+  // outer.iFlushMaster.out.head._1 <> cyclotron.io.flush.i
+  // outer.dFlushMaster.out.head._1 <> cyclotron.io.flush.d
+
+  // TODO: core/clusterId
+  // cyclotron.io.coreId := outer.cyclotronParams.coreId.U
+  // cyclotron.io.clusterId := outer.cyclotronParams.clusterId.U
+
+  // TODO: softReset
+  val softReset = outer.softResetFinishSlave.in.head._1.softReset
+  // cyclotron.io.softReset := softReset
+  outer.softResetFinishSlave.in.head._1.finished := cyclotron.io.finished
+
+  outer.reportCease(None)
+  outer.reportWFI(None)
+
+  when (outer.muonParams.disabled.B /* TODO: || softReset */) {
+    cyclotron.io.imem.req.ready := false.B
+    cyclotron.io.imem.resp.valid := false.B // responses will be dropped
+    outer.icacheWordNode.out.foreach(_._1.a.valid := false.B)
+  }
+
+  // TODO: perf
+}

src/main/scala/radiance/muon/MuonTile.scala

@@ -65,6 +65,7 @@ class WithMuonCores(
   crossing: RocketCrossingParams,
   standalone: Boolean,
   noILP: Boolean,
+  cyclotron: Boolean,
   difftest: Boolean,
   disabled: Boolean,
   l0i: Option[DCacheParams],
@@ -109,6 +110,7 @@ class WithMuonCores(
         dcache = l0d,
         l1CacheLineBytes = clusterParams.l1Config.blockBytes,
         peripheralAddr = clusterParams.baseAddr + clusterParams.peripheralAddrOffset,
+        cyclotron = cyclotron,
         disabled = disabled,
       )
       List.tabulate(n)(i => MuonTileAttachParams(
@@ -127,7 +129,7 @@ class WithMuonCores(
   // constructor override that omits `crossing`
   def this(n: Int, location: HierarchicalLocation = InSubsystem,
     standalone: Boolean = false, noILP: Boolean = false,
-    difftest: Boolean = false, disabled: Boolean = false,
+    cyclotron: Boolean = false, difftest: Boolean = false, disabled: Boolean = false,
     l0i: Option[DCacheParams] = None, l0d: Option[DCacheParams] = None)
   = this(n, location, RocketCrossingParams(
     master = HierarchicalElementMasterPortParams.locationDefault(location),
@@ -136,7 +138,7 @@ class WithMuonCores(
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     },
-  ), standalone, noILP, difftest, disabled, l0i, l0d)
+  ), standalone, noILP, cyclotron, difftest, disabled, l0i, l0d)
 }
 
 class WithCyclotronCores(

src/main/scala/radiance/subsystem/Configs.scala

@@ -926,7 +926,7 @@ object Cyclotron {
   }
 
   def unflatten(destWord: UInt, flattened: UInt, index: Int): Unit = {
-    assert(destWord.widthKnown)
+    assert(destWord.widthKnown, "cannot unflatten to sink with unknown width")
     destWord := splitUInt(flattened, destWord.getWidth)(index)
   }
 }
@@ -1049,51 +1049,62 @@ class CyclotronTile(implicit p: Parameters) extends CoreModule {
     val finished = Output(Bool())
   })
 
-  val bbox = Module(new CyclotronTileBlackBox)
+  val bbox = Module(new CyclotronTileBlackBox(this))
   bbox.io.clock := clock
   bbox.io.reset := reset.asBool
 
   import Cyclotron._
 
   // imem
-  io.imem.req.ready := bbox.io.imem_req_ready
-  bbox.io.imem_req_valid := io.imem.req.valid
-  bbox.io.imem_req_bits_address := io.imem.req.bits.address
-  bbox.io.imem_req_bits_tag := io.imem.req.bits.tag
-  bbox.io.imem_resp_ready := io.imem.resp.ready
-  io.imem.resp.valid := bbox.io.imem_resp_valid
-  io.imem.resp.bits.tag := bbox.io.imem_resp_bits_tag
-  io.imem.resp.bits.data := bbox.io.imem_resp_bits_data
-  io.imem.resp.bits.metadata := DontCare
+  bbox.io.imem_req_ready := io.imem.req.ready
+  io.imem.req.valid := bbox.io.imem_req_valid
+  io.imem.req.bits.address := bbox.io.imem_req_bits_address
+  io.imem.req.bits.tag := bbox.io.imem_req_bits_tag
+  io.imem.req.bits.size := log2Ceil(muonParams.instBits / 8).U
+  io.imem.req.bits.store := false.B
+  io.imem.req.bits.data := 0.U
+  io.imem.req.bits.mask := ((1 << muonParams.instBytes) - 1).U
+  io.imem.resp.ready := bbox.io.imem_resp_ready
+  bbox.io.imem_resp_valid := io.imem.resp.valid
+  bbox.io.imem_resp_bits_tag := io.imem.resp.bits.tag
+  bbox.io.imem_resp_bits_data := io.imem.resp.bits.data
 
   // dmem
-  // TODO: dedup with CyclotronDataMem?
-  bbox.io.dmem_req_valid := VecInit(io.dmem.req.map(_.valid)).asUInt
-  bbox.io.dmem_req_bits_store := VecInit(io.dmem.req.map(_.bits.store)).asUInt
-  bbox.io.dmem_req_bits_tag := VecInit(io.dmem.req.map(_.bits.tag)).asUInt
-  bbox.io.dmem_req_bits_address := VecInit(io.dmem.req.map(_.bits.address)).asUInt
-  bbox.io.dmem_req_bits_size := VecInit(io.dmem.req.map(_.bits.size)).asUInt
-  bbox.io.dmem_req_bits_data := VecInit(io.dmem.req.map(_.bits.data)).asUInt
-  bbox.io.dmem_req_bits_mask := VecInit(io.dmem.req.map(_.bits.mask)).asUInt
-  bbox.io.dmem_resp_ready := VecInit(io.dmem.resp.map(_.ready)).asUInt
   io.dmem.req.zipWithIndex.foreach { case (req, i) =>
-    req.ready := bbox.io.dmem_req_ready(i)
+    req.valid := bbox.io.dmem_req_valid(i)
+    req.bits.store := bbox.io.dmem_req_bits_store(i)
+    unflatten(req.bits.tag, bbox.io.dmem_req_bits_tag, i)
+    unflatten(req.bits.address, bbox.io.dmem_req_bits_address, i)
+    unflatten(req.bits.size, bbox.io.dmem_req_bits_size, i)
+    unflatten(req.bits.data, bbox.io.dmem_req_bits_data, i)
+    unflatten(req.bits.mask, bbox.io.dmem_req_bits_mask, i)
   }
+  bbox.io.dmem_req_ready := VecInit(io.dmem.req.map(_.ready)).asUInt
+
+  bbox.io.dmem_resp_valid := VecInit(io.dmem.resp.map(_.valid)).asUInt
+  bbox.io.dmem_resp_bits_tag := VecInit(io.dmem.resp.map(_.bits.tag)).asUInt
+  bbox.io.dmem_resp_bits_data := VecInit(io.dmem.resp.map(_.bits.data)).asUInt
   io.dmem.resp.zipWithIndex.foreach { case (resp, i) =>
-    resp.valid := bbox.io.dmem_resp_valid(i)
-    unflatten(resp.bits.tag, bbox.io.dmem_resp_bits_tag, i)
-    unflatten(resp.bits.data, bbox.io.dmem_resp_bits_data, i)
+    resp.ready := bbox.io.dmem_resp_ready(i)
     resp.bits.metadata := DontCare
   }
 
   io.finished := bbox.io.finished
 }
 
-class CyclotronTileBlackBox(implicit p: Parameters) extends CyclotronBlackBox
-with HasBlackBoxResource with HasCoreParameters {
+class CyclotronTileBlackBox(outer: CyclotronTile)(implicit val p: Parameters)
+  extends BlackBox(Map(
+    "ARCH_LEN"       -> outer.archLen,
+    "INST_BITS"      -> outer.muonParams.instBits,
+    "IMEM_TAG_BITS"  -> outer.imemTagBits,
+    "DMEM_DATA_BITS" -> outer.archLen,
+    "DMEM_TAG_BITS"  -> outer.dmemTagBits,
+    "NUM_LANES"      -> outer.numLanes,
+  )) with HasBlackBoxResource with HasCoreParameters {
   val io = IO(new Bundle {
     val clock = Input(Clock())
     val reset = Input(Bool())
+
     val imem_req_valid = Output(Bool())
     val imem_req_ready = Input(Bool())
     val imem_req_bits_address = Output(UInt(addressBits.W))