scoreboard: Fix missing rsRead/rsWrite rollback on failure

Author: hansungk

src/main/scala/radiance/muon/Hazard.scala

@@ -67,9 +67,11 @@ class Hazard(implicit p: Parameters) extends CoreModule()(p) {
     rsAdmit.valid := uopValid && !hasWAW && !hasWAR
     if (muonParams.debug) {
       when (uopValid && hasWAR) {
-        printf(cf"hazard: IBUF head (wid=${ibufPort.bits.uop.wid}, PC=${ibufPort.bits.uop.pc}%x) is gated RS admission due to WAR\n")
+        printf(cf"hazard: IBUF head (wid=${ibufPort.bits.uop.wid}, PC=${ibufPort.bits.uop.pc}%x, " +
+               cf"rd=${ibufPort.bits.uop.inst.rd}) is gated RS admission due to WAR\n")
       }.elsewhen (uopValid && hasWAW) {
-        printf(cf"hazard: IBUF head (wid=${ibufPort.bits.uop.wid}, PC=${ibufPort.bits.uop.pc}%x) is gated RS admission due to WAW\n")
+        printf(cf"hazard: IBUF head (wid=${ibufPort.bits.uop.wid}, PC=${ibufPort.bits.uop.pc}%x), " +
+               cf"rd=${ibufPort.bits.uop.inst.rd}) is gated RS admission due to WAW\n")
       }
     }
 

src/main/scala/radiance/muon/Scoreboard.scala

@@ -312,8 +312,13 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) {
       printf(cf"scoreboard: received RS update (warp=${warpId}) ")
       printUpdate(warpIo.updateRS)
 
-      commitUpdate(rsReadRecs, isWrite = false)
-      commitUpdate(rsWriteRecs, isWrite = true)
+      when (rsSuccess) {
+        commitUpdate(rsReadRecs, isWrite = false)
+        commitUpdate(rsWriteRecs, isWrite = true)
+      }.otherwise {
+        commitUpdate(collRecs, isWrite = false)
+        commitUpdate(wbRecs, isWrite = true)
+      }
 
       when (!rsReadSuccess) {
         printf(cf"scoreboard: warp=${warpId}: failed to commit RS update due to read overflow: ")

src/test/scala/radiance/ScoreboardTest.scala

@@ -238,6 +238,34 @@ class ScoreboardTest extends AnyFlatSpec {
     }
   }
 
+  it should "unroll both pendingReads and Writes if either counter has overflown" in {
+    val p = testParams()
+    simulate(new Scoreboard()(p)) { c =>
+      reset(c)
+      clearIO(c)
+
+      setUpdate(c.io.hazard(0).updateRS, pReg = 42, incr = true, decr = false, doWrite = true, doRead = false)
+      c.io.hazard(0).updateRS.success.expect(true.B)
+      c.clock.step()
+
+      c.io.hazard(0).readRs1.enable.poke(true.B)
+      c.io.hazard(0).readRs1.pReg.poke(42.U)
+      c.io.hazard(0).readRs1.pendingReads.expect(0.U)
+      c.io.hazard(0).readRs1.pendingWrites.expect(1.U)
+
+      setUpdate(c.io.hazard(0).updateRS, pReg = 42, incr = true, decr = false, doWrite = true, doRead = true)
+      c.io.hazard(0).updateRS.success.expect(false.B)
+      c.clock.step()
+
+      clearIO(c)
+
+      c.io.hazard(0).readRs1.enable.poke(true.B)
+      c.io.hazard(0).readRs1.pReg.poke(42.U)
+      c.io.hazard(0).readRs1.pendingReads.expect(0.U)
+      c.io.hazard(0).readRs1.pendingWrites.expect(1.U)
+    }
+  }
+
   it should "fail if pendingReads/pendingWrites counter has underflown" in {
     val p = testParams()
     simulate(new Scoreboard()(p)) { c =>