Parameterize bypass; rename to noILP

Author: hansungk

chipyard/RadianceConfigs.scala

@@ -152,10 +152,10 @@ class RadianceMuonConfig extends Config(
 
 class RadianceTapeoutSimConfig extends Config(
   // new WithRadianceMxGemmini(location = InCluster(1), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
-  new WithMuonCores(2, location = InCluster(1), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig)) ++
+  new WithMuonCores(2, location = InCluster(1), noILP = true, l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig)) ++
   new WithRadianceCluster(1, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
   // new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
-  new WithMuonCores(2, location = InCluster(0), l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig)) ++
+  new WithMuonCores(2, location = InCluster(0), noILP = true, l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig)) ++
   new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
   new WithExtGPUMem() ++
   new freechips.rocketchip.rocket.WithCFlushEnabled ++ // thanks kevin

src/main/scala/radiance/muon/Backend.scala

@@ -41,8 +41,8 @@ class Backend(
   scoreboard.io.updateColl <> reservStation.io.scb.updateColl
   scoreboard.io.updateWB <> reservStation.io.scb.updateWB
 
-  val bypass = true
-  val issued = if (bypass) {
+  val noILP = muonParams.noILP
+  val issued = if (noILP) {
     hazard.reset := true.B
     scoreboard.reset := true.B
     reservStation.reset := true.B
@@ -77,8 +77,8 @@ class Backend(
   val regs = Seq(Rs1, Rs2, Rs3)
   val collector = Module(new DuplicatedCollector)
   collector.io.readReq.valid := collector.io.readReq.bits.anyEnabled()
-  if (bypass) {
-    // on bypass, manage collector entirely after issue
+  if (noILP) {
+    // on noILP, manage collector entirely after issue
     (haves lazyZip regs lazyZip collector.io.readData.regs lazyZip collector.io.readReq.bits.regs)
       .foreach { case (has, reg, readData, collReq) =>
         val pReg = issued.bits.uop.inst(reg)
@@ -126,7 +126,7 @@ class Backend(
   execute.io.mem.smem <> io.smem
   execute.io.lsuReserve <> io.lsuReserve
 
-  if (bypass) {
+  if (noILP) {
     // fallback issue: stall every instruction until writeback
     // or execute req fire, for instructions that don't need writeback (i.e. stores, fences)
     val inFlight = RegInit(false.B)
@@ -155,7 +155,7 @@ class Backend(
     execute.io.req.valid := inFlight && !hasIssued
 
     // assumes 1-cycle latency collector
-    // FIXME: this changes issue-vs-execute timing on bypass=true/false, which
+    // FIXME: this changes issue-vs-execute timing on noILP=true/false, which
     // is confusing
     val uop = RegEnable(issued.bits.uop, 0.U.asTypeOf(issued.bits.uop.cloneType), issued.fire)
     val token = RegEnable(issued.bits.token, 0.U.asTypeOf(issued.bits.token.cloneType), issued.fire)

src/main/scala/radiance/muon/MuonCore.scala

@@ -32,10 +32,12 @@ case class MuonCoreParams(
   // issue
   numIssueQueueEntries: Int = 8, // RS
   maxPendingReads: Int = 3,      // scoreboard
+  noILP: Boolean = false, // fallback to single-in-flight instruction issue
+                          // logic ("bypass")
   // collector
-  // if true, use a bank-conflict-avoiding operand collector
-  // if false, use a simple rs1/2/3-duplicated register file
-  useCollector: Boolean = false,
+  useCollector: Boolean = false,  // if true, use a bank-conflict-avoiding
+                                  // operand collector; if false, use a simple
+                                  // rs1/2/3-duplicated register file
   numRegBanks: Int = 1,          // when useCollector true
   numCollectorEntries: Int = 1,  // when useCollector true
   // execute

src/main/scala/radiance/muon/Scoreboard.scala

@@ -36,7 +36,6 @@ class ScoreboardHazardIO(implicit p: Parameters) extends CoreBundle()(p) {
   val readRs2  = new ScoreboardRead(scoreboardReadCountBits, scoreboardWriteCountBits)
   val readRs3  = new ScoreboardRead(scoreboardReadCountBits, scoreboardWriteCountBits)
   val readRd   = new ScoreboardRead(scoreboardReadCountBits, scoreboardWriteCountBits)
-  // TODO: per-warp ports
 }
 
 /** Scoreboard module keeps track of pending reads and writes to every register
@@ -193,8 +192,6 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) {
       val newCount = WireDefault(currCount)
 
       // skip x0 updates
-      //
-      // TODO: refactor; handling both incr / decr seems overkill
       when (u.pReg =/= 0.U) {
         // if currCount + u.incr overflows but u.decr cancels it out, treat
         // it as a success.

src/main/scala/radiance/subsystem/Configs.scala

@@ -64,6 +64,7 @@ class WithMuonCores(
   location: HierarchicalLocation,
   crossing: RocketCrossingParams,
   standalone: Boolean,
+  noILP: Boolean,
   difftest: Boolean,
   disabled: Boolean,
   l0i: Option[DCacheParams],
@@ -80,6 +81,7 @@ class WithMuonCores(
       numLanes = up(SIMTCoreKey).get.numLanes,
       numCores = n,
       numClusters = 2, // TODO: magic number
+      noILP = noILP,
       logSMEMInFlights = log2Ceil(up(SIMTCoreKey).get.numSMEMInFlights),
       lsu = LoadStoreUnitParams(
         numLsuLanes = up(SIMTCoreKey).get.numLsuLanes
@@ -124,16 +126,17 @@ class WithMuonCores(
 }) {
   // constructor override that omits `crossing`
   def this(n: Int, location: HierarchicalLocation = InSubsystem,
-           standalone: Boolean = false, difftest: Boolean = false, disabled: Boolean = false,
-          l0i: Option[DCacheParams] = None, l0d: Option[DCacheParams] = None)
+    standalone: Boolean = false, noILP: Boolean = false,
+    difftest: Boolean = false, disabled: Boolean = false,
+    l0i: Option[DCacheParams] = None, l0d: Option[DCacheParams] = None)
   = this(n, location, RocketCrossingParams(
     master = HierarchicalElementMasterPortParams.locationDefault(location),
     slave = HierarchicalElementSlavePortParams.locationDefault(location),
     mmioBaseAddressPrefixWhere = location match {
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     },
-  ), standalone, difftest, disabled, l0i, l0d)
+  ), standalone, noILP, difftest, disabled, l0i, l0d)
 }
 
 class WithCyclotronCores(

src/main/scala/radiance/unittest/Configs.scala

@@ -33,6 +33,12 @@ class MuonCoreTestConfig extends Config(
   new WithSIMTConfig(numWarps = 8, numLanes = 16, numLsuLanes = 16, numSMEMInFlights = 4) ++
   new BaseSubsystemConfig)
 
+class MuonCoreNoILPTestConfig extends Config(
+  new WithMuonUnitTestHarness(new MuonCoreTest()(_)) ++
+  new WithMuonCores(1, standalone = true, noILP = true, difftest = true) ++
+  new WithSIMTConfig(numWarps = 8, numLanes = 16, numLsuLanes = 16, numSMEMInFlights = 4) ++
+  new BaseSubsystemConfig)
+
 class MuonCoreTestNoDiffConfig extends Config(
   new WithMuonUnitTestHarness(new MuonCoreTest()(_)) ++
   new WithMuonCores(1, standalone = true, difftest = false) ++