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hansungkhansungk
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Filter debug prints by level
1 parent 3f2bd4e commit b5cb8ed

5 files changed

Lines changed: 71 additions & 48 deletions

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‎src/main/scala/radiance/muon/Collector.scala‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,11 @@ object CollectorResponse {
4949
}
5050
}
5151

52+
object CollectorDebug {
53+
val collDebugLevel = 2
54+
}
55+
import CollectorDebug.collDebugLevel
56+
5257
class CollectorOperandRead(implicit p: Parameters) extends CoreBundle()(p) {
5358
val collEntryWidth = log2Up(muonParams.numCollectorEntries)
5459
val hasPReg = !muonParams.useCollector
@@ -123,20 +128,20 @@ class DuplicatedCollector(implicit p: Parameters) extends CoreModule()(p) with H
123128
when (io.readReq.fire) {
124129
when (freeNow) {
125130
// concurrent alloc/free; reuse id being freed
126-
debugf(cf"collector: concurrently alloc/freeing id=${rdCollEntry}. before: ")
131+
debugf(collDebugLevel, cf"collector: concurrently alloc/freeing id=${rdCollEntry}. before: ")
127132
allocTable.print
128133

129134
nextAllocId := rdCollEntry
130135
}.otherwise {
131136
val (succ, allocId) = allocTable.alloc
132-
debugf(cf"collector: allocating id=${allocId}. before: ")
137+
debugf(collDebugLevel, cf"collector: allocating id=${allocId}. before: ")
133138
allocTable.print
134139

135140
assert(succ, "unexpected collector alloc fail")
136141
nextAllocId := allocId
137142
}
138143
}.elsewhen (freeNow) {
139-
debugf(cf"collector: freeing id=${rdCollEntry}. before: ")
144+
debugf(collDebugLevel, cf"collector: freeing id=${rdCollEntry}. before: ")
140145
allocTable.print
141146

142147
allocTable.free(rdCollEntry)
@@ -277,11 +282,11 @@ extends HasCoreParameters with HasDebugPrint {
277282
}
278283

279284
def print = {
280-
debugfAppend("table content: ")
285+
debugfAppend(collDebugLevel, "table content: ")
281286
(0 until numEntries).foreach { i =>
282-
debugfAppend(cf"${table(i).valid}")
287+
debugfAppend(collDebugLevel, cf"${table(i).valid}")
283288
}
284-
debugfAppend("\n")
289+
debugfAppend(collDebugLevel, "\n")
285290
}
286291
}
287292

‎src/main/scala/radiance/muon/LSU.scala‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,11 @@ import radiance.muon.AddressSpaceCfg._
88
import radiance.memory.MultiReadOneWriteSRAM
99
import org.chipsalliance.cde.config.Field
1010

11+
object LSUDebug {
12+
val lsuDebugLevel = 2
13+
}
14+
import LSUDebug.lsuDebugLevel
15+
1116
case class LoadStoreUnitParams(
1217
val numLsuLanes: Int = 16, // width of downstream memory interface and writeback; width of execute fixed to # of lanes
1318

@@ -464,7 +469,7 @@ class LoadStoreQueue(implicit p: Parameters) extends CoreModule()(p) with HasDeb
464469

465470

466471
val debugIdMsg = io.debugId.map(x => cf"${x}").getOrElse(cf"n/a")
467-
debugf(
472+
debugf(lsuDebugLevel,
468473
cf"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Enqueue (LDQ: ${loadQueue}): " +
469474
cf"warp = ${warpId}, index = ${idxBits(tail)}, " +
470475
cf"op = ${io.op}, otherTail = ${io.otherTail}, debugId = ${debugIdMsg}\n"
@@ -1216,7 +1221,7 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) with HasDebu
12161221
metadataMemW.data := metadata
12171222
metadataMemW.enable := true.B
12181223

1219-
debugf(cf"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Operands / metadata update: " +
1224+
debugf(lsuDebugLevel, cf"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Operands / metadata update: " +
12201225
cf"token = ${io.coreReq.bits.token}, (hex value = 0x${Hexadecimal(io.coreReq.bits.token.asUInt)}), " +
12211226
cf"address = ${address}, " +
12221227
cf"destReg = ${io.coreReq.bits.destReg}, " +
@@ -1362,7 +1367,7 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) with HasDebu
13621367
io.addressSpace := token.addressSpace
13631368

13641369
when (io.memRequest.fire) {
1365-
debugf(p"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Mem request sent: " +
1370+
debugf(lsuDebugLevel, p"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Mem request sent: " +
13661371
p"tag=0x${Hexadecimal(tag.asUInt)}, " +
13671372
p"packet=${packet}, " +
13681373
p"tmask=${Binary(io.memRequest.bits.tmask.asUInt)}, " +
@@ -1466,15 +1471,15 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) with HasDebu
14661471
loadDataMemW.enable := false.B
14671472

14681473
when (receivedResp) {
1469-
debugf(p"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Mem response received: " +
1474+
debugf(lsuDebugLevel, p"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Mem response received: " +
14701475
p"tag=0x${Hexadecimal(respTag.token.asUInt)}, " +
14711476
p"packet=${respTag.packet}, " +
14721477
p"resp valids=${Binary(respValidsVec.asUInt)}, " +
14731478
p"data = ${loadDataWriteVal}\n"
14741479
)
14751480

14761481
when (shouldWriteLoadData) {
1477-
debugf(p"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Load Data updated: idx=${loadDataWriteIdx}, val=${loadDataWriteVal}\n")
1482+
debugf(lsuDebugLevel, p"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] Load Data updated: idx=${loadDataWriteIdx}, val=${loadDataWriteVal}\n")
14781483

14791484
loadDataMemW.address := loadDataWriteIdx
14801485
loadDataMemW.data := loadDataWriteVal
@@ -1546,7 +1551,7 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) with HasDebu
15461551
completionWrite := newCompletion
15471552
}
15481553

1549-
debugf(cf"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] completion updated: " +
1554+
debugf(lsuDebugLevel, cf"[LSU clid=${idIO.clusterId} cid=${idIO.coreId}] completion updated: " +
15501555
cf"packet=${respTag_d1.packet}, " +
15511556
cf"new valids=${newCompletion}, " +
15521557
cf"prev valids=${completion_d1}, " +
@@ -1657,7 +1662,7 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) with HasDebu
16571662
if (lsuDerived.debugIdBits.isDefined) {
16581663
io.coreResp.bits.debugId.get := s2_req.debugId.get
16591664
when (io.coreResp.fire) {
1660-
debugf(cf"[LsuWriteback clid=${idIO.clusterId} cid=${idIO.coreId}] coreResp debugId = ${io.coreResp.bits.debugId.get}\n")
1665+
debugf(lsuDebugLevel, cf"[LsuWriteback clid=${idIO.clusterId} cid=${idIO.coreId}] coreResp debugId = ${io.coreResp.bits.debugId.get}\n")
16611666
}
16621667
}
16631668

@@ -1676,7 +1681,7 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) with HasDebu
16761681

16771682
when (io.coreResp.fire) {
16781683
val debugIdMsg = io.coreResp.bits.debugId.map(x => cf"${x}").getOrElse(cf"n/a")
1679-
debugf(
1684+
debugf(lsuDebugLevel,
16801685
cf"[LsuWriteback clid=${idIO.clusterId} cid=${idIO.coreId}] coreResp fire: debugId = ${debugIdMsg}, tmask = ${io.coreResp.bits.tmask}, " +
16811686
cf"writebackData = ${io.coreResp.bits.writebackData}, warpId = ${io.coreResp.bits.warpId}, " +
16821687
cf"destReg = ${io.coreResp.bits.destReg}, packet = ${io.coreResp.bits.packet} (metadata = ${s2_metadata})\n"
@@ -1734,7 +1739,7 @@ class LSUCoreAdapter(implicit p: Parameters) extends CoreModule()(p) with HasDeb
17341739
lsuReq.ready := allReady
17351740

17361741
when (lsuReq.fire) {
1737-
debugf(p"[LSUCoreAdapter clid=${idIO.clusterId} cid=${idIO.coreId}] Core request sent: " +
1742+
debugf(lsuDebugLevel, p"[LSUCoreAdapter clid=${idIO.clusterId} cid=${idIO.coreId}] Core request sent: " +
17381743
p"tag=0x${Hexadecimal(lsuReq.bits.tag)}, " +
17391744
p"tmask=${Binary(lsuReq.bits.tmask.asUInt)}, " +
17401745
p"lane valids=${Binary(Cat(laneValids.reverse))}, " +
@@ -1763,7 +1768,7 @@ class LSUCoreAdapter(implicit p: Parameters) extends CoreModule()(p) with HasDeb
17631768
lsuResp.bits.data := respData
17641769

17651770
when (respValids.orR) {
1766-
debugf(p"[LSUCoreAdapter clid=${idIO.clusterId} cid=${idIO.coreId}] Core responses: " +
1771+
debugf(lsuDebugLevel, p"[LSUCoreAdapter clid=${idIO.clusterId} cid=${idIO.coreId}] Core responses: " +
17671772
p"valids=${Binary(Cat(respValids.reverse))}, " +
17681773
p"leader=${leader}, " +
17691774
p"leaderTag=0x${Hexadecimal(leaderLsuTag)}, " +

‎src/main/scala/radiance/muon/MuonCore.scala‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ case class MuonCoreParams(
5555
barrierBits: Int = 4,
5656
// dev
5757
debug: Boolean = true, // enable debug-only printfs and hardware constructs
58+
debugLevel: Int = 1, // max debug level to print
5859
trace: Boolean = false, // enable instruction trace generation
5960
profiler: Boolean = true, // enable performance profiling report generation
6061
difftest: Boolean = false // enable arch-state differential testing
@@ -269,11 +270,12 @@ trait HasDebugPrint extends HasCoreParameters {
269270
protected def debugContext: Option[DebugContext] = None
270271

271272
private def printPrefix(ctx: DebugContext): Unit = {
272-
printf("[Muon c%d.%d @%d] ", ctx.clusterId, ctx.coreId, ctx.cycle)
273+
// 64-bit gives too much whitespace
274+
printf("[Muon c%d.%d @%d] ", ctx.clusterId, ctx.coreId, ctx.cycle(31, 0))
273275
}
274276

275-
def debugf(pable: Printable): Unit = {
276-
if (muonParams.debug) {
277+
def debugf(level: Int, pable: Printable): Unit = {
278+
if (muonParams.debug && level <= muonParams.debugLevel) {
277279
debugContext match {
278280
case Some(ctx) => printPrefix(ctx)
279281
case None => printf("[@?] ")
@@ -282,11 +284,15 @@ trait HasDebugPrint extends HasCoreParameters {
282284
}
283285
}
284286

285-
def debugfAppend(pable: Printable): Unit = {
286-
if (muonParams.debug) {
287+
def debugf(pable: Printable): Unit = debugf(1, pable)
288+
289+
def debugfAppend(level: Int, pable: Printable): Unit = {
290+
if (muonParams.debug && level <= muonParams.debugLevel) {
287291
printf(pable)
288292
}
289293
}
294+
295+
def debugfAppend(pable: Printable): Unit = debugfAppend(1, pable)
290296
}
291297

292298
trait HasDebugContext extends HasDebugPrint { this: Module =>

‎src/main/scala/radiance/muon/ReservationStation.scala‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,8 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) with Ha
101101
uop.inst.rs3))
102102
}
103103

104+
val rsDebugLevel = 1
105+
104106
// ---------
105107
// admission
106108
// ---------
@@ -125,7 +127,8 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) with Ha
125127
collFiredTable(emptyRow) := VecInit.fill(Isa.maxNumRegs)(false.B)
126128
collPtrTable(emptyRow) := 0.U
127129

128-
debugf(cf"RS: admitted: warp=${io.admit.bits.ibufEntry.uop.wid}, " +
130+
debugf(rsDebugLevel,
131+
cf"RS: admitted: warp=${io.admit.bits.ibufEntry.uop.wid}, " +
129132
cf"PC=${io.admit.bits.ibufEntry.uop.pc}%x at row ${emptyRow}\n")
130133
printTable
131134
}
@@ -221,7 +224,8 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) with Ha
221224
val newFired = (collFiredTable(collRow) zip io.collector.readReq.bits.regs.map(_.enable))
222225
.map { case (a,b) => a || b }
223226
collFiredTable(collRow) := newFired
224-
debugf(cf"RS: collector request fired at row:${collRow}, warp:${collUop.wid}, pc:${collUop.pc}%x\n")
227+
debugf(rsDebugLevel,
228+
cf"RS: collector request fired at row:${collRow}, warp:${collUop.wid}, pc:${collUop.pc}%x\n")
225229
}
226230

227231
// upon collector response:
@@ -266,7 +270,8 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) with Ha
266270
scbPort.incr := false.B
267271
scbPort.decr := (rs =/= 0.U)
268272

269-
debugf(cf"RS: collector response handled at row:${i}, " +
273+
debugf(rsDebugLevel,
274+
cf"RS: collector response handled at row:${i}, " +
270275
cf"warp:${instTable(i).uop.wid}, pc:${instTable(i).uop.pc}%x, " +
271276
cf"collEntry:${io.collector.readResp.bits.collEntry}, " +
272277
cf"rs:${rs}, rsi:${rsi}\n")

‎src/main/scala/radiance/muon/Scoreboard.scala‎

Lines changed: 26 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
6363
// TODO: reads epoch
6464
}
6565

66+
val sbDebugLevel = 2
67+
6668
// flip-flops
6769
val readTable = RegInit(VecInit.fill(muonParams.numPhysRegs)(0.U(scoreboardReadCountBits.W)))
6870
val writeTable = RegInit(VecInit.fill(muonParams.numPhysRegs)(0.U(scoreboardWriteCountBits.W)))
@@ -200,7 +202,7 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
200202
newCount := currCount + u.incr - u.decr
201203
}
202204

203-
debugf(cf"applyUpdates: [${debug}] ${countName} pReg:${u.pReg}, newCount:${newCount}, currCount:${currCount}, incr:${u.incr}(${u.incr.getWidth}W), decr:${u.decr}(${u.decr.getWidth}W), success:${success}, overflow:${overflow}, underflow:${underflow}\n")
205+
debugf(sbDebugLevel, cf"applyUpdates: [${debug}] ${countName} pReg:${u.pReg}, newCount:${newCount}, currCount:${currCount}, incr:${u.incr}(${u.incr.getWidth}W), decr:${u.decr}(${u.decr.getWidth}W), success:${success}, overflow:${overflow}, underflow:${underflow}\n")
204206

205207
// underflow should never be possible since the number of retired
206208
// regs should strictly be smaller than the pending regs, i.e. no
@@ -210,7 +212,7 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
210212
// cf"scoreboard: ${countName} underflow at pReg=${u.pReg} " +
211213
// cf"(currCount=${currCount}, incr=${u.incr}, decr=${u.decr})")
212214
}.elsewhen (u.incr === u.decr && u.incr =/= 0.U) {
213-
debugf(cf"applyUpdates: [${debug}] ${countName} incr/decr cancel; pReg:${u.pReg}, newCount: ${newCount}, currCount: ${currCount}(${currCount.getWidth}W), incr:${u.incr}(${u.incr.getWidth}W), decr:${u.decr}(${u.decr.getWidth}W)\n")
215+
debugf(sbDebugLevel, cf"applyUpdates: [${debug}] ${countName} incr/decr cancel; pReg:${u.pReg}, newCount: ${newCount}, currCount: ${currCount}(${currCount.getWidth}W), incr:${u.incr}(${u.incr.getWidth}W), decr:${u.decr}(${u.decr.getWidth}W)\n")
214216
}
215217
}
216218

@@ -242,10 +244,10 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
242244
when (r.dirty) {
243245
assert(r.pReg =/= 0.U, "update to x0 not filtered in the logic?")
244246
if (isWrite) {
245-
debugf(cf"scoreboard: committed write (pReg:${r.pReg}, new pendingWrites:${r.counter})\n")
247+
debugf(sbDebugLevel, cf"scoreboard: committed write (pReg:${r.pReg}, new pendingWrites:${r.counter})\n")
246248
writeTable(r.pReg) := r.counter
247249
} else {
248-
debugf(cf"scoreboard: committed read (pReg:${r.pReg}, new pendingReads:${r.counter})\n")
250+
debugf(sbDebugLevel, cf"scoreboard: committed read (pReg:${r.pReg}, new pendingReads:${r.counter})\n")
249251
readTable(r.pReg) := r.counter
250252
}
251253
}
@@ -273,7 +275,7 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
273275
io.hazard.updateRS.success := io.hazard.updateRS.enable && rsSuccess
274276

275277
when (io.hazard.updateRS.enable) {
276-
debugf(cf"scoreboard: received RS update ")
278+
debugf(sbDebugLevel, cf"scoreboard: received RS update ")
277279
printUpdate(io.hazard.updateRS)
278280

279281
// these contain coll/wb updates
@@ -286,29 +288,29 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
286288
}
287289

288290
when (!rsReadSuccess) {
289-
debugf(cf"scoreboard: failed to commit RS update due to read overflow: ")
291+
debugf(sbDebugLevel, cf"scoreboard: failed to commit RS update due to read overflow: ")
290292
printUpdate(io.hazard.updateRS)
291293
}.elsewhen (!rsWriteSuccess) {
292-
debugf(cf"scoreboard: failed to commit RS update due to write overflow: ")
294+
debugf(sbDebugLevel, cf"scoreboard: failed to commit RS update due to write overflow: ")
293295
printUpdate(io.hazard.updateRS)
294296
}
295297

296-
debugf(cf"scoreboard: table received RS update; content beforehand:\n")
298+
debugf(sbDebugLevel, cf"scoreboard: table received RS update; content beforehand:\n")
297299
printTable
298300
}.elsewhen (io.updateWB.enable || io.updateColl.enable) {
299301
when (io.updateWB.enable) {
300-
debugf("scoreboard: received WB update ")
302+
debugf(sbDebugLevel, "scoreboard: received WB update ")
301303
printUpdate(io.updateWB)
302304
}
303305
when (io.updateColl.enable) {
304-
debugf("scoreboard: received coll update ")
306+
debugf(sbDebugLevel, "scoreboard: received coll update ")
305307
printUpdate(io.updateColl)
306308
}
307309

308310
commitUpdate(collRecs, isWrite = false)
309311
commitUpdate(wbRecs, isWrite = true)
310312

311-
debugf(cf"scoreboard: table received coll/WB update; content beforehand:\n")
313+
debugf(sbDebugLevel, cf"scoreboard: table received coll/WB update; content beforehand:\n")
312314
printTable
313315
}
314316

@@ -338,39 +340,39 @@ class Scoreboard(implicit p: Parameters) extends CoreModule()(p) with HasDebugCo
338340

339341
def printUpdate(upd: ScoreboardUpdate) = {
340342
def printReg(reg: ScoreboardRegUpdate) = {
341-
debugfAppend(cf"{pReg:${reg.pReg}, incr:")
343+
debugfAppend(sbDebugLevel, cf"{pReg:${reg.pReg}, incr:")
342344
when (reg.incr) {
343-
debugfAppend("1")
345+
debugfAppend(sbDebugLevel, "1")
344346
}.elsewhen (reg.decr) {
345-
debugfAppend("-1")
347+
debugfAppend(sbDebugLevel, "-1")
346348
}.otherwise {
347-
debugfAppend("0")
349+
debugfAppend(sbDebugLevel, "0")
348350
}
349-
debugfAppend("}")
351+
debugfAppend(sbDebugLevel, "}")
350352
}
351353

352-
debugfAppend("{rs1: ")
354+
debugfAppend(sbDebugLevel, "{rs1: ")
353355
printReg(upd.reads(0))
354-
debugfAppend(", rs2: ")
356+
debugfAppend(sbDebugLevel, ", rs2: ")
355357
printReg(upd.reads(1))
356-
debugfAppend(", rs3: ")
358+
debugfAppend(sbDebugLevel, ", rs3: ")
357359
printReg(upd.reads(2))
358-
debugfAppend(", rd: ")
360+
debugfAppend(sbDebugLevel, ", rd: ")
359361
printReg(upd.write)
360-
debugfAppend("}\n")
362+
debugfAppend(sbDebugLevel, "}\n")
361363
}
362364

363365
def printTable = {
364366
// @perf: NOTE: this can instantiate a read port for *every* table entries;
365367
// make sure to guard this with debug
366-
debugf("=" * 8 + " Scoreboard " + "=" * 8 + "\n")
368+
debugf(sbDebugLevel, "=" * 8 + " Scoreboard " + "=" * 8 + "\n")
367369
for (i <- 0 until muonParams.numPhysRegs) {
368370
val reads = readTable(i)
369371
val writes = writeTable(i)
370372
when (reads > 0.U || writes > 0.U) {
371-
debugf(cf"p${i} | writes:${writes} | reads:${reads}\n")
373+
debugf(sbDebugLevel, cf"p${i} | writes:${writes} | reads:${reads}\n")
372374
}
373375
}
374-
debugf("=" * 28 + "\n")
376+
debugf(sbDebugLevel, "=" * 28 + "\n")
375377
}
376378
}

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