perf: Make cyclesDispatched count RS occupancy not admission

Author: hansungk

src/main/scala/radiance/muon/Backend.scala

@@ -53,20 +53,20 @@ class Backend(implicit p: Parameters) extends CoreModule()(p) {
     reservStation.io.issue
   }
 
-  val cyclesDispatched = PerfCounter(reservStation.io.admit.fire)
   val cyclesEligible = PerfCounter(issued.valid)
   val cyclesIssued = PerfCounter(issued.fire)
 
+  val cyclesDispatched = reservStation.io.perf.cyclesDispatched
   io.perf.cyclesDispatched := cyclesDispatched
-  io.perf.cyclesEligible := cyclesEligible
+  io.perf.cyclesEligible := reservStation.io.perf.cyclesEligible
   io.perf.cyclesIssued := cyclesIssued
   io.perf.perWarp.zipWithIndex.foreach { case (p, wid) =>
     p.cyclesDispatched :=
       PerfCounter(reservStation.io.admit.fire &&
                   (reservStation.io.admit.bits.ibufEntry.uop.wid === wid.U))
-    p.stallsRSFull := reservStation.io.perf(wid).stallsRSFull
+    p.stallsRSFull := reservStation.io.perf.perWarp(wid).stallsRSFull
 
-    p.cyclesEligible := reservStation.io.perf(wid).cyclesEligible
+    p.cyclesEligible := reservStation.io.perf.perWarp(wid).cyclesEligible
     p.cyclesIssued := PerfCounter(issued.fire && (issued.bits.uop.wid === wid.U))
     // LSU business is accounted for at the IBUF, not at the EX stage; it needs
     // to be added separately

src/main/scala/radiance/muon/ReservationStation.scala

@@ -35,10 +35,15 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) {
       val readResp = Flipped(CollectorResponse(Isa.maxNumRegs, isWrite = false))
       val readData = Flipped(new CollectorOperandRead)
     }
-    val perf = Output(Vec(numWarps, new Bundle {
+    val perf = Output(new Bundle {
+      val cyclesDispatched = Perf.T
       val cyclesEligible = Perf.T
-      val stallsRSFull = Perf.T
-    }))
+      val perWarp = Vec(numWarps, new Bundle {
+        val cyclesDispatched = Perf.T
+        val cyclesEligible = Perf.T
+        val stallsRSFull = Perf.T
+      })
+    })
   })
 
   val numEntries = muonParams.numIssueQueueEntries
@@ -101,7 +106,7 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) {
   val rowEmptyVec = VecInit((0 until numEntries).map(!validTable(_)))
   val hasEmptyRow = rowEmptyVec.reduce(_ || _)
   io.admit.ready := hasEmptyRow
-  io.perf.zipWithIndex.foreach { case (p, wid) =>
+  io.perf.perWarp.zipWithIndex.foreach { case (p, wid) =>
     p.stallsRSFull :=
       PerfCounter(io.admit.valid && !hasEmptyRow &&
                   io.admit.bits.ibufEntry.uop.wid === wid.U)
@@ -125,6 +130,15 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) {
   val rsOccupancy = WireDefault(PopCount(validTable))
   dontTouch(rsOccupancy)
 
+  io.perf.cyclesDispatched := PerfCounter(rsOccupancy =/= 0.U)
+  io.perf.perWarp.zipWithIndex.foreach { case (p, wid) =>
+    val validThisWarp = (0 until numEntries).map { i =>
+      validTable(i) && (instTable(i).uop.wid === wid.U)
+    }
+    val hasThisWarp = validThisWarp.reduce(_ || _)
+    p.cyclesDispatched := PerfCounter(hasThisWarp)
+  }
+
   // -----------------
   // collector control
   // -----------------
@@ -353,7 +367,9 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) {
   dontTouch(issuedId)
 
   // connect per-warp eligible perf counters
-  io.perf.zipWithIndex.foreach { case (p, wid) =>
+  val hasEligible = eligibles.map(_.valid).reduce(_ || _)
+  io.perf.cyclesEligible := PerfCounter(hasEligible)
+  io.perf.perWarp.zipWithIndex.foreach { case (p, wid) =>
     val eligiblesThisWarp = eligibles.map { row =>
       row.valid && (row.bits.entry.uop.wid === wid.U)
     }