Merge branch 'main' of https://github.com/ucb-bar/radiance

Author: richardyrh

cyclotron

@@ -252,10 +252,12 @@ to the value of `rs2` of the "leader" lane, i.e. the left-most active lane.
 vx_spawn rs1, rs2
 ```
 
-Activates warps 1 up to the value of `rs1` in the "leader" lane, if not already active. Has no effect on warp 0.
-Sets `PC` of newly active warps to the value of `rs2` in the "leader" lane. Sets tmask of newly active warps to all 1's.  
+Activates warps `[0, rs1)`, except the warp that executed this instruction, and
+sets their `PC` to `rs2`.  Sets tmask of newly active warps to all 1's.
+The values of `rs1` and `rs2` are taken from the "leader" lane.
 
-Note: this will eventually be superceded by command processor + neutrino
+Note: `vx_wspawn` eventually be superceded by command processor's scheduling
+capabilities.
 
 ## New Registers
 

docs/isa.md

@@ -597,6 +597,8 @@ void cyclotron_trace(
 
 void cyclotron_difftest_reg_rs(
     const uint8_t   trace_sim_tick,
+    const uint32_t  cluster_id,
+    const uint32_t  core_id,
     const uint8_t   trace_valid,
     const uint32_t  trace_pc,
     const uint32_t  trace_warpId,
@@ -614,6 +616,8 @@ void cyclotron_difftest_reg_rs(
 
 void cyclotron_difftest_reg(
     const uint8_t   trace_sim_tick,
+    const uint32_t  cluster_id,
+    const uint32_t  core_id,
     const uint8_t   trace_valid,
     const uint32_t  trace_pc,
     const uint32_t  trace_warpId,
@@ -630,6 +634,8 @@ void cyclotron_difftest_reg(
 ) {
   cyclotron_difftest_reg_rs(
     trace_sim_tick,
+    cluster_id,
+    core_id,
     trace_valid,
     trace_pc,
     trace_warpId,

src/main/resources/csrc/Cyclotron.cc

@@ -1,4 +1,6 @@
 module CyclotronDiffTestBlackBox #(
+  parameter CLUSTER_ID = 0,
+  parameter CORE_ID = 0,
   parameter ARCH_LEN = 32,
   parameter INST_BITS = 64,
   parameter NUM_WARPS = 8,
@@ -37,6 +39,8 @@ module CyclotronDiffTestBlackBox #(
 
   import "DPI-C" function cyclotron_difftest_reg(
     input bit  trace_sim_tick,
+    input int  cluster_id,
+    input int  core_id,
     input bit  trace_valid,
     input int  trace_pc,
     input int  trace_warpId,
@@ -73,6 +77,8 @@ module CyclotronDiffTestBlackBox #(
     end else begin
       cyclotron_difftest_reg(
         SIM_TICK,
+        CLUSTER_ID,
+        CORE_ID,
         trace_valid,
         trace_pc,
         trace_warpId,

src/main/resources/vsrc/CyclotronDiffTest.v

@@ -226,10 +226,10 @@ class Backend(implicit p: Parameters) extends CoreModule()(p) {
   collector.io.writeReq.bits.regs.head.enable := exRegWbFire
   collector.io.writeReq.bits.regs.head.pReg := exRegWb.bits.rd
   collector.io.writeReq.bits.regs.head.data.get := exRegWb.bits.data
+  collector.io.writeReq.bits.regs.head.tmask.get := exRegWb.bits.tmask
   collector.io.writeReq.bits.pc.foreach(_ := 0.U /* bogus */)
   collector.io.writeReq.bits.rsEntryId := 0.U // TODO: writes don't need to allocate RS entry; remove this
   collector.io.writeReq.valid := collector.io.writeReq.bits.anyEnabled()
-  // TODO: tmask
   dontTouch(collector.io)
 
   // debug

src/main/scala/radiance/muon/Backend.scala

@@ -12,8 +12,8 @@ class CollectorRequest(
   val regs = Vec(numPorts, new Bundle {
     val enable = Bool()
     val pReg = pRegT
+    val tmask = Option.when(isWrite)(tmaskT)
     val data = Option.when(isWrite)(Vec(numLanes, regDataT))
-    // TODO: tmask
   })
   val rsEntryId = UInt(rsEntryIdWidth.W)
   val pc = Option.when(muonParams.debug)(pcT)
@@ -39,7 +39,6 @@ class CollectorResponse(
   val collEntry = UInt(collEntryWidth.W)
   val regs = Vec(numPorts, new Bundle {
     val enable = Bool()
-    // TODO: tmask
   })
 }
 
@@ -58,14 +57,14 @@ class CollectorOperandRead(implicit p: Parameters) extends CoreBundle()(p) {
     val collEntry = UInt(collEntryWidth.W)
     val regs = Vec(Isa.maxNumRegs, new Bundle {
       val enable = Bool()
+      // TODO: tmask for @power
     })
   }))
   // same-cycle as `req`
   val resp = Valid(Vec(Isa.maxNumRegs, new Bundle {
     val enable = Bool()
     val pReg = Option.when(hasPReg)(pRegT)
     val data = Vec(numLanes, regDataT)
-    // TODO: tmask
   }))
 }
 
@@ -92,7 +91,7 @@ class DuplicatedCollector(implicit p: Parameters) extends CoreModule()(p) {
 
   def vecRegDataT = Vec(numLanes, regDataT)
   val vecZeros = 0.U.asTypeOf(vecRegDataT)
-  val rfBanks = Seq.fill(Isa.maxNumRegs)(Seq.fill(muonParams.numRegBanks)(SRAM(
+  val rfBanks = Seq.fill(Isa.maxNumRegs)(Seq.fill(muonParams.numRegBanks)(SRAM.masked(
     size = muonParams.numPhysRegs / muonParams.numRegBanks,
     tpe = vecRegDataT,
     numReadPorts = 1,
@@ -166,7 +165,13 @@ class DuplicatedCollector(implicit p: Parameters) extends CoreModule()(p) {
       val regOut = Mux(nextPReg =/= 0.U,
         VecInit(bankPorts.map(_.data))(nextBankId),
         vecZeros)
-      // TODO: @perf: Skip latching 0.U to collBank
+
+      // latch SRAM output to collector banks
+      //
+      // TODO: @power: Respect readReq.tmask, and latch 0.U for inactive lanes.
+      // Currently the downstream EX does the right thing even when the
+      // collector supplies garbage values for inactive lanes, but this is
+      // better for power.
       collBank.zipWithIndex.foreach { case (entry, i) =>
         when (nextEn && (i.U === nextAllocId)) {
           entry := regOut
@@ -189,14 +194,19 @@ class DuplicatedCollector(implicit p: Parameters) extends CoreModule()(p) {
   io.writeReq.ready := true.B
   val writeEnable = io.writeReq.fire && io.writeReq.bits.regs.head.enable
   val writePReg = io.writeReq.bits.regs.head.pReg
+  val writeTmask = io.writeReq.bits.regs.head.tmask.get
   val writeData = io.writeReq.bits.regs.head.data.get
-  // write to all of rs1/2/3 banks
+  // broadcast write to all of rs1/2/3 banks
   rfBanks.foreach { case banks =>
     val bankWrites = VecInit(banks.map(_.writePorts.head))
-    bankWrites.foreach { b =>
-      b.address := regBankAddr(writePReg)
-      b.data := writeData
-      b.enable := false.B
+    bankWrites.foreach { port =>
+      port.address := regBankAddr(writePReg)
+      port.data := writeData
+      assert(port.mask.isDefined, "RegFile SRAM must be masked")
+      assert(port.mask.get.length == writeTmask.getWidth,
+             "RegFile SRAM mask width does not match tmask width")
+      port.mask.get := VecInit(writeTmask.asBools)
+      port.enable := false.B
     }
     bankWrites(regBankId(writePReg)).enable := writeEnable && (writePReg =/= 0.U)
   }

src/main/scala/radiance/muon/Collector.scala

@@ -405,7 +405,11 @@ class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
   // RTL-model difftest
   if (core.muonParams.difftest) {
     assert(isSim, "muon traces cannot enabled in non-sim mode!")
-    val cdiff = Module(new CyclotronDiffTest(tick = true))
+    val cdiff = Module(new CyclotronDiffTest(
+      clusterId = outer.muonParams.clusterId,
+      coreId = outer.muonParams.coreId,
+      tick = true
+    ))
     cdiff.io.trace <> core.io.trace.get
   }
 }

src/main/scala/radiance/muon/MuonTile.scala

@@ -172,10 +172,11 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) {
   io.collector.readReq.valid := collValid
   // this is clunky, but Mem does not support partial-field updates
   (collOpNeed lazyZip collRegs lazyZip io.collector.readReq.bits.regs)
-    .zipWithIndex.foreach { case ((need, pReg, cReq), rsi) =>
-      assert(cReq.data.isEmpty) // isRead
-      cReq.enable := collValid && need
-      cReq.pReg := Mux(need, pReg, 0.U)
+    .zipWithIndex.foreach { case ((need, pReg, readReqReg), rsi) =>
+      assert(readReqReg.data.isEmpty) // isRead
+      assert(readReqReg.tmask.isEmpty) // isRead
+      readReqReg.enable := collValid && need
+      readReqReg.pReg := Mux(need, pReg, 0.U)
     }
   io.collector.readReq.bits.rsEntryId := collRow
   io.collector.readReq.bits.pc.foreach(_ := collPC)

src/main/scala/radiance/muon/ReservationStation.scala

@@ -275,18 +275,19 @@ class WarpScheduler(implicit p: Parameters)
         wspawnMask.asBools.zipWithIndex.map { case (en, wid) =>
           when(en) {
             when (!pcTracker(wid).valid) {
-              // only set thread mask if warp not already active
-              threadMasks(wid) := fullThreadMask
-            }
-            when ((io.commit.bits.wid === wid.U) || (!pcTracker(wid).valid)) {
-              // set pc if warp is
-              // (1) initiator of wspawn or
+              // set pc and tmask if warp is
+              // (1) not the initiator of wspawn and
               // (2) was not already active before
               pcTracker(wid).bits := wspawn.bits.pc
               pcTracker(wid).valid := true.B
+              threadMasks(wid) := fullThreadMask
               // spawning(wid) := true.B
               stallTracker.unstall(wid.U)
             }
+            when (io.commit.bits.wid === wid.U) {
+              assert(pcTracker(wid).valid === true.B)
+              stallTracker.unstall(wid.U)
+            }
           }
         }
      }

src/main/scala/radiance/muon/WarpScheduler.scala

@@ -20,6 +20,7 @@ import radiance.memory._
 import radiance.muon._
 import radiance.virgo.{NumVortexCores, VirgoClusterParams, VortexCoreParams, VortexL1Key}
 import radiance.muon.LoadStoreUnitParams
+import radiance.unittest.CyclotronLinked
 
 sealed trait RadianceSmemSerialization
 case object FullySerialized extends RadianceSmemSerialization
@@ -66,6 +67,7 @@ class WithMuonCores(
   standalone: Boolean,
   noILP: Boolean,
   trace: Boolean,
+  /** cyclotron-as-a-tile: use golden core model */
   cyclotron: Boolean,
   difftest: Boolean,
   disabled: Boolean,
@@ -94,6 +96,9 @@ class WithMuonCores(
       difftest = difftest,
     )
   }
+  case CyclotronLinked => {
+    up(CyclotronLinked) || site(RadianceSimArgs) || trace || difftest || cyclotron
+  }
   case TilesLocated(`location`) => {
     if (standalone) {
       Seq()