Merge branch 'main' of https://github.com/ucb-bar/radiance

Author: richardyrh

cyclotron

@@ -338,44 +338,47 @@ void cyclotron_mem(
 };
 
 void cyclotron_difftest_reg_rs(
-    const uint8_t   regTest_valid,
-    const uint32_t  regTest_pc,
-    const uint8_t   regTest_regs_0_enable,
-    const uint8_t   regTest_regs_0_address,
-    const uint32_t *regTest_regs_0_data,
-    const uint8_t   regTest_regs_1_enable,
-    const uint8_t   regTest_regs_1_address,
-    const uint32_t *regTest_regs_1_data,
-    const uint8_t   regTest_regs_2_enable,
-    const uint8_t   regTest_regs_2_address,
-    const uint32_t *regTest_regs_2_data
+    const uint8_t   trace_valid,
+    const uint32_t  trace_pc,
+    const uint32_t  trace_warpId,
+    const uint8_t   trace_regs_0_enable,
+    const uint8_t   trace_regs_0_address,
+    const uint32_t *trace_regs_0_data,
+    const uint8_t   trace_regs_1_enable,
+    const uint8_t   trace_regs_1_address,
+    const uint32_t *trace_regs_1_data,
+    const uint8_t   trace_regs_2_enable,
+    const uint8_t   trace_regs_2_address,
+    const uint32_t *trace_regs_2_data
 );
 
 void cyclotron_difftest_reg(
-    const uint8_t   regTest_valid,
-    const uint32_t  regTest_pc,
-    const uint8_t   regTest_regs_0_enable,
-    const uint8_t   regTest_regs_0_address,
-    const uint32_t *regTest_regs_0_data,
-    const uint8_t   regTest_regs_1_enable,
-    const uint8_t   regTest_regs_1_address,
-    const uint32_t *regTest_regs_1_data,
-    const uint8_t   regTest_regs_2_enable,
-    const uint8_t   regTest_regs_2_address,
-    const uint32_t *regTest_regs_2_data
+    const uint8_t   trace_valid,
+    const uint32_t  trace_pc,
+    const uint32_t  trace_warpId,
+    const uint8_t   trace_regs_0_enable,
+    const uint8_t   trace_regs_0_address,
+    const uint32_t *trace_regs_0_data,
+    const uint8_t   trace_regs_1_enable,
+    const uint8_t   trace_regs_1_address,
+    const uint32_t *trace_regs_1_data,
+    const uint8_t   trace_regs_2_enable,
+    const uint8_t   trace_regs_2_address,
+    const uint32_t *trace_regs_2_data
 ) {
   cyclotron_difftest_reg_rs(
-    regTest_valid,
-    regTest_pc,
-    regTest_regs_0_enable,
-    regTest_regs_0_address,
-    regTest_regs_0_data,
-    regTest_regs_1_enable,
-    regTest_regs_1_address,
-    regTest_regs_1_data,
-    regTest_regs_2_enable,
-    regTest_regs_2_address,
-    regTest_regs_2_data
+    trace_valid,
+    trace_pc,
+    trace_warpId,
+    trace_regs_0_enable,
+    trace_regs_0_address,
+    trace_regs_0_data,
+    trace_regs_1_enable,
+    trace_regs_1_address,
+    trace_regs_1_data,
+    trace_regs_2_enable,
+    trace_regs_2_address,
+    trace_regs_2_data
   );
 }
 

src/main/resources/csrc/Cyclotron.cc

@@ -11,6 +11,7 @@ import "DPI-C" function string vpi_get_binary();
 import "DPI-C" function cyclotron_difftest_reg(
   input bit  trace_valid,
   input int  trace_pc,
+  input int  trace_warpId,
   input bit  trace_regs_0_enable,
   input byte trace_regs_0_address,
   input int  trace_regs_0_data[NUM_LANES],

src/main/resources/vsrc/Cyclotron.vh

@@ -18,6 +18,7 @@ module CyclotronDiffTestBlackBox #(
 
   input  logic                            trace_valid,
   input  logic [ARCH_LEN-1:0]             trace_pc,
+  input  logic [WARP_ID_BITS-1:0]         trace_warpId,
   input  logic                            trace_regs_0_enable,
   input  logic [REG_BITS-1:0]             trace_regs_0_address,
   input  logic [(NUM_LANES*ARCH_LEN)-1:0] trace_regs_0_data,
@@ -36,6 +37,7 @@ module CyclotronDiffTestBlackBox #(
   // need to be in ascending order to match with C array memory layout
   bit     __out_trace_valid;
   int     __out_trace_pc;
+  int     __out_trace_warpId;
   bit     __out_trace_regs_0_enable;
   byte    __out_trace_regs_0_address;
   int     __out_trace_regs_0_data [0:NUM_LANES-1];
@@ -61,6 +63,7 @@ module CyclotronDiffTestBlackBox #(
   // connect regtrace signals
   assign __out_trace_valid = trace_valid;
   assign __out_trace_pc = trace_pc;
+  assign __out_trace_warpId = trace_warpId;
   assign __out_trace_regs_0_enable  = trace_regs_0_enable;
   assign __out_trace_regs_0_address = trace_regs_0_address;
   assign __out_trace_regs_1_enable  = trace_regs_1_enable;
@@ -82,6 +85,7 @@ module CyclotronDiffTestBlackBox #(
       cyclotron_difftest_reg(
         __out_trace_valid,
         __out_trace_pc,
+        __out_trace_warpId,
         __out_trace_regs_0_enable,
         __out_trace_regs_0_address,
         __out_trace_regs_0_data,

src/main/resources/vsrc/CyclotronDiffTest.v

@@ -102,6 +102,7 @@ class Backend(
   io.trace.foreach { traceIO =>
     traceIO.valid := issued.fire
     traceIO.bits.pc := issued.bits.uop.pc
+    traceIO.bits.warpId := issued.bits.uop.wid
     (traceIO.bits.regs zip operands)
       .zipWithIndex.foreach { case ((tReg, opnd), rsi) =>
         tReg.enable := issued.bits.uop.inst(haves(rsi))

src/main/scala/radiance/muon/Backend.scala

@@ -288,6 +288,7 @@ class InstMemIO(implicit val p: Parameters) extends ParameterizedBundle()(p) wit
  *  issue time. */
 class TraceIO()(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = pcT
+  val warpId = widT
   val regs = Vec(Isa.maxNumRegs, new Bundle {
     val enable = Bool()
     val address = pRegT

src/main/scala/radiance/muon/MuonCore.scala

@@ -14,6 +14,7 @@ import org.chipsalliance.diplomacy.lazymodule.LazyModule
 import radiance.cluster.SoftResetFinishNode
 import radiance.memory._
 import radiance.subsystem._
+import radiance.unittest.CyclotronDiffTest
 
 case object NumMuonCores extends Field[Int](0)
 
@@ -297,8 +298,8 @@ class MuonTile(
 }
 
 class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
+  val muon = Module(new MuonCore(test = true))
 
-  val muon = Module(new MuonCore())
   MuonMemTL.connectTL(muon.io.imem.req, muon.io.imem.resp, outer.icacheWordNode)
 
   MuonMemTL.multiConnectTL(muon.io.dmem.req, muon.io.dmem.resp, outer.innerLsuNodes)
@@ -315,4 +316,7 @@ class MuonTileModuleImp(outer: MuonTile) extends BaseTileModuleImp(outer) {
 
   muon.io.softReset := outer.softResetFinishSlave.in.head._1.softReset
   outer.softResetFinishSlave.in.head._1.finished := muon.io.finished
+
+  val cdiff = Module(new CyclotronDiffTest)
+  cdiff.io.trace <> muon.io.trace.get
 }

src/main/scala/radiance/muon/MuonTile.scala

@@ -968,6 +968,7 @@ class CyclotronDiffTest(implicit p: Parameters) extends CoreModule {
 
   cbox.io.trace.valid := io.trace.valid
   cbox.io.trace.pc := io.trace.bits.pc
+  cbox.io.trace.warpId := io.trace.bits.warpId
   (cbox.io.trace.regs zip io.trace.bits.regs).foreach { case (boxtr, tr) =>
     boxtr.enable := tr.enable
     boxtr.address := tr.address
@@ -984,6 +985,7 @@ with HasBlackBoxResource with HasCoreParameters {
     val trace = Input(new Bundle {
       val valid = Bool()
       val pc = pcT
+      val warpId = widT
       val regs = Vec(Isa.maxNumRegs, new Bundle {
         val enable = Bool()
         val address = pRegT

src/main/scala/radiance/unittest/Muon.scala

@@ -129,9 +129,10 @@ def finalize_test(test: RunningTest, status: int) -> int:
             return 1
 
         errstring = log_has_error(test.log_path).rstrip("\n")
-        if status == 0 and errstring:
-            print(f"[{myname}] FAIL: {test.elf}")
-            print(f"{errstring}")
+        if status != 0 or errstring:
+            print(f"[{myname}] FAIL: {test.elf} (status: {status})")
+            if errstring:
+                print(f"{errstring}")
             return 1
         return status
     finally: