@@ -35,7 +35,7 @@ class SFUPipe(implicit p: Parameters) extends ExPipe(true, true) {
3535
3636 case class StallFields [T <: Data ](
3737 inProgress : Valid [T ],
38- writeback : Valid [SchedWriteback ],
38+ storedWriteback : Valid [SchedWriteback ],
3939 start : Bool ,
4040 done : T => Bool ,
4141 reqSent : Bool ,
@@ -44,7 +44,7 @@ class SFUPipe(implicit p: Parameters) extends ExPipe(true, true) {
4444 def this (start : Bool , done : T => Bool , reqT : T ) = {
4545 this (
4646 inProgress = RegInit (0 .U .asTypeOf(Valid (reqT))),
47- writeback = RegInit (0 .U .asTypeOf(schedWritebackT)),
47+ storedWriteback = RegInit (0 .U .asTypeOf(schedWritebackT)),
4848 start = start,
4949 done = done,
5050 reqSent = RegInit (false .B ),
@@ -54,7 +54,7 @@ class SFUPipe(implicit p: Parameters) extends ExPipe(true, true) {
5454
5555 when (start) {
5656 inProgress.valid := true .B
57- writeback := writeback
57+ storedWriteback := writeback
5858 assert(! reqSent)
5959 }
6060
@@ -271,10 +271,10 @@ class SFUPipe(implicit p: Parameters) extends ExPipe(true, true) {
271271
272272
273273 // arbitrate writeback port for both barriers and fences
274- val stallRespArbiter = Module (new RRArbiter (barriers.head.writeback.cloneType , stalls.length))
274+ val stallRespArbiter = Module (new RRArbiter (schedWritebackT , stalls.length))
275275 (stallRespArbiter.io.in zip stalls).foreach { case (arbIn, s) =>
276276 arbIn.valid := s.respReceived && s.inProgress.valid
277- arbIn.bits := s.writeback
277+ arbIn.bits := s.storedWriteback
278278 when (arbIn.fire) {
279279 s.inProgress.valid := false .B
280280 s.reqSent := false .B
@@ -298,6 +298,6 @@ class SFUPipe(implicit p: Parameters) extends ExPipe(true, true) {
298298
299299 // override busy
300300 when (io.req.fire) {
301- busy := ! inst.b(IsNuInvoke )
301+ busy := ! inst.b(IsNuInvoke ) && ! inst.b( IsFenceI ) && ! inst.b( IsFenceD )
302302 }
303303}
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