faet: add storeReady in RS

Author: yizishun

rtl/src/backend/Backend.scala

@@ -188,6 +188,7 @@ class Backend(val parameter: BackendParameter)
   issue.io.intrInfo       <> execute.io.intrInfo
   issue.io.storeOut       := execute.io.storeOut
   issue.io.uncachedOut    := execute.io.uncachedOut
+  issue.io.storeReady    := execute.io.storeReady
   // [Pipeline 3] Regfile and ROB Read (in Issue Module)
   //
   // [Pipeline 4] Execute

rtl/src/backend/execute/Execute.scala

@@ -130,6 +130,7 @@ class ExecuteInterface(parameter: ExecuteParameter) extends Bundle {
   val difftestStableCounter =
     if (parameter.aluBlockParameter.enableDifftest) Some(Output(UInt(64.W)))
     else None
+  val storeReady = Output(Bool())
 }
 
 /** Hardware Implementation of Execute */
@@ -179,6 +180,7 @@ class Execute(val parameter: ExecuteParameter)
   lsuBlock.io.uncachedCommit := io.uncachedCommit
   io.icacopOut               := lsuBlock.io.icacopOut
   io.cacheInfo               <> lsuBlock.io.cacheInfo
+  io.storeReady              := lsuBlock.io.storeReady
 
   // difftest
   if (parameter.mduBlockParameter.enableDifftest) {

rtl/src/backend/execute/fu/LsuBlock.scala

@@ -206,6 +206,7 @@ class RawLsuBlockIO(parameter: LsuBlockParameter) extends Bundle {
   val memWrResp = Vec(2, Flipped(Decoupled(new MemWrResp())))
 
   val icacopOut = Valid(new ICacheOp(parameter.addressWidth))
+  val storeReady = Output(Bool())
 }
 
 class LsuBlockIO(parameter: LsuBlockParameter) extends Bundle {

rtl/src/backend/issue/Issue.scala

@@ -115,6 +115,7 @@ class IssueInterface(parameter: IssueParameter) extends Bundle {
         parameter.pRegNum,
         parameter.robSize,
         parameter.enableDifftest)))
+  val storeReady = Input(Bool())
   val uncachedOut = Flipped(
     Output(
       Vec(
@@ -232,6 +233,7 @@ class Issue(val parameter: IssueParameter) extends Module with SerializableModul
   scheduler.io.normalWakeupBusIn := dataPath.io.normalWakeupBusOut
   scheduler.io.lsuWakeupBusIn    := dataPath.io.lsuWakeupBusOut
   scheduler.io.redirect          := io.redirect
+  scheduler.io.storeReady          := io.storeReady
   dataPath.io.cacheInfo          := cacheInfo
   dataPath.io.writeBack          <> io.writeBack
   dataPath.io.writeBackData      := writeBackData

rtl/src/backend/issue/ReservationStation.scala

@@ -163,6 +163,8 @@ class ReservationStation(parameter: ReservationStationParameter, issueParameter:
     val redirect = Input(Valid(new RedirectIO(issueParameter.robSize, issueParameter.brSize)))
     // [Fence]
     val canRunFence = Input(Bool())
+    // [store Ready]
+    val storeReady = if (parameter.name == "LSU") Some(Input(Bool())) else None
     // [Debug]
     val debug =
       if (issueParameter.debug)
@@ -265,7 +267,7 @@ class ReservationStation(parameter: ReservationStationParameter, issueParameter:
       // lsu group issue
       val firstStore = PriorityEncoder(
         rsData.map(e => e.valid && (!e.rfWen || e.func === LsuOp.SCW.asUInt)))
-      baseReady && srcReady && (idx.U <= firstStore) // || !entry.rfWen 其实可以同一个周期选出多条store，但是前提是第一条store被选出来，但是现在的条件肯定不行，但是再多一点条件路径会很长
+      baseReady && srcReady && (Mux(io.storeReady.get, idx.U <= firstStore, idx.U < firstStore)) // || !entry.rfWen 其实可以同一个周期选出多条store，但是前提是第一条store被选出来，但是现在的条件肯定不行，但是再多一点条件路径会很长
     } else {
       baseReady && srcReady
     }

rtl/src/backend/issue/Scheduler.scala

@@ -99,6 +99,8 @@ class Scheduler(parameter: IssueParameter) extends Module {
     val redirect = Input(Valid(new RedirectIO(parameter.robSize, parameter.brSize))) // replay
     val robDeqPtr = if (parameter.debug) Some(Input(new RobPtr(parameter.robSize))) else None
     val robEnqPtr = if (parameter.debug) Some(Input(new RobPtr(parameter.robSize))) else None
+    
+    val storeReady = Input(Bool())
   })
   // prepare dispatch data [Dispatch] -----------------
   val dispatchData = WireDefault(io.dispatchData)
@@ -134,6 +136,7 @@ class Scheduler(parameter: IssueParameter) extends Module {
   }
   // lsu should be treated as group issue due to order requirement
   lsuRs.io.canDeqUpdate.foreach { _ := io.deqData.lsu.map(_.ready).reduce(_ && _) }
+  lsuRs.io.storeReady.get := io.storeReady
 
   // wakeup bus [Wakeup] -----------------
   val wbWakeupBus = Wire(Vec(parameter.lsuRSParameter.fuNum, ValidIO(new WakeupBus(parameter))))

rtl/src/backend/rob/ROB.scala

@@ -801,7 +801,7 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
     exceptionHandler.bits.robIdx := Mux(shouldCommitException(deqPtr.value), deqPtr, deqPtr - 1.U)
     exceptionHandler.bits.brIdx  := robInstInfoRdDeqWire(0).brIdx
     exceptionHandler.bits.ecode  := exceptionInfo(deqPtr.value).ecodes
-    canSampleIntr                := true.B // unlock
+    canSampleIntr                := RegNext(true.B) // unlock
   }
   // [IcacheOp]
   io.icacheOpBranchInfo.valid := false.B