fix(lsu): now storebuffer's valid is correct

X-Actions-Control: difftest

Signed-off-by: Woshiluo Luo <woshiluo.luo@outlook.com>

Author: woshiluo

rtl/src/backend/execute/fu/lsu/dcache/store/StoreBuffer.scala

@@ -87,19 +87,18 @@ class StoreBuffer(val parameter: LsuBlockParameter) extends Module {
   }
 
   // Redirect
-  val redirectValidList = VecInit((0 until parameter.bufferLength).map(i => {
-    val currentPtr = headPtr + (parameter.bufferLength - i - 1).U
-    bufferQueue(currentPtr.value).attr.valid &
-      bufferQueue(currentPtr.value).attr.upstream.brIdx <= io.redirectPtr.bits &
-      currentPtr < tailPtr
+  val redirectList = VecInit((0 until parameter.bufferLength).map(i => {
+    bufferQueue(i).attr.valid &
+      bufferQueue(i).attr.upstream.brIdx > io.redirectPtr.bits &
+      io.redirectPtr.valid
   }))
-  val maxHeadPtrOffset =
-    Mux(
-      redirectValidList.asUInt.orR,
-      PriorityEncoder(redirectValidList.asUInt),
-      parameter.bufferLength.U)
-  val maxTailPtr  = headPtr + (parameter.bufferLength.U - maxHeadPtrOffset)
-  val baseTailPtr = Mux(io.redirectPtr.valid, maxTailPtr, tailPtr)
+  val redirectCount = PopCount(redirectList)
+  for (i <- 0 until parameter.bufferLength) {
+    when(redirectList(i)) {
+      bufferQueue(i).attr.valid := false.B
+    }
+  }
+  val baseTailPtr = tailPtr - redirectCount
 
   // EnQueue
   private val canEnque =