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Revert "fix: int will not care excp"
This reverts commit 8af0b30.
1 parent 3d3b451 commit 6197056

1 file changed

Lines changed: 2 additions & 5 deletions

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rtl/src/backend/rob/ROB.scala

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -617,7 +617,6 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
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io.writeBackData.lsuWriteBack.ready := true.B
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val intrNoReg = RegInit(0.U(13.W))
620-
val sampleInt = Wire(Bool())
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def shouldCommitException(idx: UInt): Bool =
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exceptionInfo(idx).ecodes === ECodes.SYS ||
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exceptionInfo(idx).ecodes === ECodes.BRK
@@ -627,7 +626,6 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
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valid(deqPtr.value) &&
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writeBacked(deqPtr.value) &&
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(robState === s_normal || robState === s_idle) &&
630-
sampleInt &&
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io.lsuCanCommit // hasException 只会存在一个周期,这一个周期会commit掉syscall指令,并将状态转移到exception状态
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/** 4.Commit */
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val commit = Wire(
@@ -831,14 +829,14 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
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io.icacheOpBranchInfo.bits.isRet := false.B
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}
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// [Interrupt]
834-
sampleInt := false.B
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intrCanCommit := true.B
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val intrNo =
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io.intrInfo.estat.is_12 ## io.intrInfo.estat.is_11 ## io.intrInfo.estat.zero1 ## io.intrInfo.estat.is_9_2 ## io.intrInfo.estat.is_1_0
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when(intrNo =/= 0.U && canSampleIntr && io.intrInfo.ie) { // lock the first intr i meet
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when(
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valid(deqPtr.value) &&
841-
((
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((!exception(deqPtr.value) &&
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exceptionInfo(deqPtr.value).ecodes === ECodes.NONE &&
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robState === s_normal &&
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writeBacked(deqPtr.value) &&
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!io.redirect.valid &&
@@ -847,7 +845,6 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
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exception(deqPtr.value) := true.B
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exceptionInfo(deqPtr.value).ecodes := ECodes.INT
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intrNoReg := intrNo
850-
sampleInt := true.B
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io.intrInfo.canSampleIntr := false.B
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canSampleIntr := false.B // lock
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intrCanCommit := false.B

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