@@ -617,7 +617,6 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
617617 io.writeBackData.lsuWriteBack.ready := true .B
618618
619619 val intrNoReg = RegInit (0 .U (13 .W ))
620- val sampleInt = Wire (Bool ())
621620 def shouldCommitException (idx : UInt ): Bool =
622621 exceptionInfo(idx).ecodes === ECodes .SYS ||
623622 exceptionInfo(idx).ecodes === ECodes .BRK
@@ -627,7 +626,6 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
627626 valid(deqPtr.value) &&
628627 writeBacked(deqPtr.value) &&
629628 (robState === s_normal || robState === s_idle) &&
630- sampleInt &&
631629 io.lsuCanCommit // hasException 只会存在一个周期,这一个周期会commit掉syscall指令,并将状态转移到exception状态
632630 /** 4.Commit */
633631 val commit = Wire (
@@ -831,14 +829,14 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
831829 io.icacheOpBranchInfo.bits.isRet := false .B
832830 }
833831 // [Interrupt]
834- sampleInt := false .B
835832 intrCanCommit := true .B
836833 val intrNo =
837834 io.intrInfo.estat.is_12 ## io.intrInfo.estat.is_11 ## io.intrInfo.estat.zero1 ## io.intrInfo.estat.is_9_2 ## io.intrInfo.estat.is_1_0
838835 when(intrNo =/= 0 .U && canSampleIntr && io.intrInfo.ie) { // lock the first intr i meet
839836 when(
840837 valid(deqPtr.value) &&
841- ((
838+ ((! exception(deqPtr.value) &&
839+ exceptionInfo(deqPtr.value).ecodes === ECodes .NONE &&
842840 robState === s_normal &&
843841 writeBacked(deqPtr.value) &&
844842 ! io.redirect.valid &&
@@ -847,7 +845,6 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
847845 exception(deqPtr.value) := true .B
848846 exceptionInfo(deqPtr.value).ecodes := ECodes .INT
849847 intrNoReg := intrNo
850- sampleInt := true .B
851848 io.intrInfo.canSampleIntr := false .B
852849 canSampleIntr := false .B // lock
853850 intrCanCommit := false .B
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