1 parent 6b6c349 commit 9221c84Copy full SHA for 9221c84
1 file changed
rtl/src/backend/execute/fu/LsuBlock.scala
@@ -524,7 +524,7 @@ class AddrTransStage(parameter: LsuBlockParameter) extends Module {
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}
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io.storeReady := reallyStoreCount <= 7.U
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- io.in.ready := allQueueReady & reallyStoreCount <= 7.U
+ io.in.ready := allQueueReady
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io.out.valid := io.out.bits.exists(x => x.valid)
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io.noLoad := ~io.out.bits.exists(x => x.valid)
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