File tree Expand file tree Collapse file tree
vtr_flow/tasks/regression_tests/vtr_reg_basic_mosaic Expand file tree Collapse file tree Original file line number Diff line number Diff line change 1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem mosaic_synth_time max_mosaic_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
2+ k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics_nolatches.v common 10.73 vpr 73.33 MiB -1 -1 -1 -1 1.09 39340 -1 -1 -1 -1 -1 -1 -1 29 99 1 0 success v8.0.0-17547-ge54109e4b4 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-110-generic x86_64 2026-08-18T20:18:42 betzgrp-pchenry /home/aliayan3/vtr-verilog-to-routing 75088 99 130 655 785 1 346 259 10 10 100 io auto 30.0 MiB 0.55 2183.88 1780 36559 8317 26755 1487 72.4 MiB 0.14 0.00 3.30624 3.18557 -521.001 -3.18557 3.18557 0.00 0.000955299 0.000855678 0.0498953 0.0450046 72.4 MiB 1.15 72.0 MiB 0.65 38 3790 23 3.92691e+06 2.11093e+06 218696. 2186.96 1.23 0.397313 0.353786 9082 42967 -1 3030 12 1055 1784 84948 26279 3.61792 3.61792 -602.534 -3.61792 0 0 278294. 2782.94 0.01 0.06 0.03 -1 -1 0.01 0.0400371 0.0374121
3+ k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 18.87 vpr 81.09 MiB -1 -1 -1 -1 2.54 43296 -1 -1 -1 -1 -1 -1 -1 50 162 0 5 success v8.0.0-17547-ge54109e4b4 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-110-generic x86_64 2026-08-18T20:18:42 betzgrp-pchenry /home/aliayan3/vtr-verilog-to-routing 83032 162 96 1359 1176 1 719 313 16 16 256 mult_36 auto 41.1 MiB 1.08 6234.36 5801 65095 15444 49196 455 81.1 MiB 0.37 0.01 16.6757 16.2113 -1177.82 -16.2113 16.2113 0.00 0.00212582 0.00195811 0.144316 0.133008 81.1 MiB 2.44 80.6 MiB 1.22 58 10100 21 1.21132e+07 4.6747e+06 904541. 3533.36 3.16 1.0234 0.944849 27572 180683 -1 9308 19 2886 5145 811395 233928 17.7691 17.7691 -1287.37 -17.7691 0 0 1.15318e+06 4504.63 0.05 0.27 0.14 -1 -1 0.05 0.117872 0.11092
4+ k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock_reader_writer.v common 5.80 vpr 59.68 MiB -1 -1 -1 -1 0.32 39996 -1 -1 -1 -1 -1 -1 -1 2 3 0 0 success v8.0.0-17547-ge54109e4b4 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-110-generic x86_64 2026-08-18T20:18:42 betzgrp-pchenry /home/aliayan3/vtr-verilog-to-routing 61108 3 1 23 24 2 8 6 4 4 16 clb auto 20.2 MiB 0.01 19 18 210 50 78 82 59.1 MiB 0.01 0.00 0.619943 0.619943 -8.40444 -0.619943 0.557849 0.01 4.9072e-05 4.2466e-05 0.0023529 0.00204305 59.1 MiB 0.14 58.6 MiB 0.08 20 17 2 107788 107788 10441.3 652.579 0.03 0.0112216 0.00975225 750 1675 -1 15 2 8 8 111 62 0.63968 0.557849 -8.29778 -0.63968 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00136144 0.00125834
Original file line number Diff line number Diff line change 1+ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem mosaic_synth_time max_mosaic_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
2+ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 287.89 vpr 322.06 MiB -1 -1 -1 -1 62.15 122208 -1 -1 -1 -1 -1 -1 -1 576 37 52 -1 success v8.0.0-17547-ge54109e4b4 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-110-generic x86_64 2026-08-18T20:18:42 betzgrp-pchenry /home/aliayan3/vtr-verilog-to-routing 329792 37 17 14329 12164 1 7951 682 38 38 1444 memory auto 299.2 MiB 10.60 99435.4 71764 192682 40573 148222 3887 322.1 MiB 5.60 0.09 7.33103 5.13361 -44568.9 -5.13361 5.13361 0.00 0.0266568 0.0204228 1.91997 1.52749 322.1 MiB 30.76 320.0 MiB 11.70 137783 17.3356 33522 4.21766 35894 109135 9303120 2160999 4.31434e+07 2.32318e+07 3.08449e+07 21360.7 15 396600 5806327 -1 5.0506 5.0506 -51544 -5.0506 0 0 4.34 -1 -1 322.1 MiB 3.33 4.83042 4.02738 299.2 MiB -1 2.68
You can’t perform that action at this time.
0 commit comments