Merge branch 'master' into swap_evaluator

Author: soheilshahrouz

doc/src/arch/reference.rst

@@ -1724,13 +1724,24 @@ A pack pattern is a power user feature directing that the CAD tool should group
 This allows the architect to help the CAD tool recognize structures that have limited flexibility so that netlist atoms that fit those structures be kept together as though they are one unit.
 This tag impacts the CAD tool only, there is no architectural impact from defining molecules.
 
-.. arch:tag:: <pack_pattern name="string" in_port="string" out_port="string"/>
+.. arch:tag:: <pack_pattern name="string" in_port="string" out_port="string" allow_multi_fanout="bool"/>
 
     .. warning:: This is a power user option. Unless you know why you need it, you probably shouldn't specify it.
 
     :req_param name: The name of the pattern.
     :req_param in_port: The input pins of the edges for this pattern.
     :req_param out_port: Which output pins of the edges for this pattern.
+    :opt_param allow_multi_fanout:
+
+        Controls whether a molecule can still be formed over this pattern connection when the netlist signal carrying it also drives other logic.
+
+        By default (``false``), the packer only matches this connection if the net driving it has exactly one sink, i.e. the signal goes straight from the source primitive to the destination primitive and nowhere else.
+        If the net fans out to additional sinks, the molecule is cut at this connection.
+
+        When set to ``true``, the packer will match this connection even if the net drives multiple sinks: the sink that fits the pattern becomes part of the molecule, and the remaining sinks are routed normally outside of it.
+        Only set this on connections where the architecture actually provides a path for that extra fanout to leave the pattern (see *Multi-fanout connections* below).
+
+        **Default:** ``false``
 
     This tag gives a hint to the CAD tool that certain architectural structures should stay together during packing.
     The tag labels interconnect edges with a pack pattern name.
@@ -1744,6 +1755,31 @@ This tag impacts the CAD tool only, there is no architectural impact from defini
     Pack patterns with more primitives take priority over pack patterns with less primitives.
     In the event that the number of primitives is the same, the pack pattern with less inputs takes priority over pack patterns with more inputs.
 
+    **Multi-fanout connections:**
+
+    By default, the prepacker assumes each pack pattern connection is point-to-point: if the netlist net implementing a connection fans out to more than one sink, no molecule is formed over that connection.
+    This is a conservative assumption — a net with extra fanout may not be routable through the dedicated intra-block interconnect the pattern describes, since the other sinks also need to be reached.
+
+    If the architecture can absorb the extra fanout (e.g., the block provides paths from the pattern connection to general routing), the architect can mark the ``<pack_pattern>`` annotation with ``allow_multi_fanout="true"``.
+    The prepacker will then form molecules over this connection even when its net drives multiple sinks; among the sinks, the one matching the pattern's destination primitive continues the molecule, and the remaining sinks are left to be routed outside the pattern.
+
+    Note that the attribute is written on individual interconnect edges, but its effect is defined at the level of a *primitive-to-primitive connection*.
+    Such a connection may pass through several interconnect edges when the two primitives are not directly wired together (e.g., the signal traverses intermediate modes or levels of the pb_type hierarchy).
+    The architect does not need to annotate every edge along that path: if any annotated edge on the connection's path is marked ``allow_multi_fanout="true"``, the entire primitive-to-primitive connection allows multi-fanout.
+
+    .. note::
+
+        If several sinks match the pattern's destination primitive, only one joins the molecule.
+        For example, with a ``LUT -> FF`` pack pattern and a LUT driving two FFs, the prepacker picks the last matching FF added to the netlist to form the molecule; the other FF is packed as a separate atom.
+
+    For example, in a carry chain where each adder's ``cout`` may also feed look-ahead logic in addition to the next adder's ``cin``, marking the chain's ``cout`` link keeps chain molecules together despite the extra fanout:
+
+    .. code-block:: xml
+
+        <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+          <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout" allow_multi_fanout="true"/>
+        </direct>
+
     **Special Case:**
 
     To specify carry chains, we use a special case of a pack pattern.

doc/src/vpr/custom_rr_graph_generator.rst

@@ -179,10 +179,6 @@ following arguments in the VPR command line:
 
 - ``--sb_maps <switch_block_map_file>``
 - ``--sb_templates <switch_block_template_directory>``
-- ``--sb_count_dir <switch_block_count_directory>`` (optional):  
-  If provided, VPR generates a CSV file for each switch block template,
-  showing how many times each switch specified in the template is used in the
-  final routing results.
 
 For additional arguments, refer to the command-line usage section in
 :ref:`vpr_command_line_usage`.

libs/libarchfpga/src/device_grid.cpp

@@ -4,6 +4,7 @@
 #include <utility>
 #include <vector>
 #include "physical_types.h"
+#include "vtr_assert.h"
 #include "vtr_expr_eval.h"
 #include "vtr_ndmatrix.h"
 #include "grid_util.h"
@@ -162,6 +163,40 @@ bool DeviceGrid::are_locs_on_same_die(t_physical_tile_loc loc_a, t_physical_tile
     return first_id == second_id;
 }
 
+bool DeviceGrid::do_locs_cross_vertical_cut(t_physical_tile_loc loc_a, t_physical_tile_loc loc_b) const {
+    VTR_ASSERT_SAFE_MSG(loc_a.layer_num == loc_b.layer_num,
+                        "This method currently always returns true if loc_a and "
+                        "loc_b are on different layers. This method takes shortcuts "
+                        "to quickly find cuts on 2D devices; it needs to be updated "
+                        "to also handle 3D devices.");
+
+    // Dice are guaranteed to be axis-aligned rectangles, so checking the die at loc_a's row
+    // is sufficient to tell whether a vertical cut separates the two locations' x coordinates;
+    // this is well-defined even when loc_a.y != loc_b.y.
+    int y = loc_a.y;
+    const DeviceDieId first_id = die_id_matrix_[loc_a.layer_num][loc_a.x][y];
+    const DeviceDieId second_id = die_id_matrix_[loc_b.layer_num][loc_b.x][y];
+
+    return first_id != second_id;
+}
+
+bool DeviceGrid::do_locs_cross_horizontal_cut(t_physical_tile_loc loc_a, t_physical_tile_loc loc_b) const {
+    VTR_ASSERT_SAFE_MSG(loc_a.layer_num == loc_b.layer_num,
+                        "This method currently always returns true if loc_a and "
+                        "loc_b are on different layers. This method takes shortcuts "
+                        "to quickly find cuts on 2D devices; it needs to be updated "
+                        "to also handle 3D devices.");
+
+    // Dice are guaranteed to be axis-aligned rectangles, so checking the die at loc_a's column
+    // is sufficient to tell whether a horizontal cut separates the two locations' y coordinates;
+    // this is well-defined even when loc_a.x != loc_b.x.
+    int x = loc_a.x;
+    const DeviceDieId first_id = die_id_matrix_[loc_a.layer_num][x][loc_a.y];
+    const DeviceDieId second_id = die_id_matrix_[loc_b.layer_num][x][loc_b.y];
+
+    return first_id != second_id;
+}
+
 DeviceDieId DeviceGrid::get_loc_die_id(t_physical_tile_loc loc) const {
     return die_id_matrix_[loc.layer_num][loc.x][loc.y];
 }

libs/libarchfpga/src/device_grid.h

@@ -325,6 +325,16 @@ class DeviceGrid {
      */
     bool are_locs_on_same_die(t_physical_tile_loc loc_a, t_physical_tile_loc loc_b) const;
 
+    /**
+     * @brief Returns true if the straight line between loc_a and loc_b crosses a vertical interposer cut.
+     */
+    bool do_locs_cross_vertical_cut(t_physical_tile_loc loc_a, t_physical_tile_loc loc_b) const;
+
+    /**
+     * @brief Returns true if the straight line between loc_a and loc_b crosses a horizontal interposer cut.
+     */
+    bool do_locs_cross_horizontal_cut(t_physical_tile_loc loc_a, t_physical_tile_loc loc_b) const;
+
     /**
      * @brief Get the die identifier of a location. In 2.5D and 3D architectures each die has its own unique identifier.
      * 

libs/libarchfpga/src/physical_types.h

@@ -1088,12 +1088,17 @@ struct t_pin_to_pin_annotation {
     std::string output_pins;
     std::string clock;
 
+    /* pack_pattern annotations only: nets on this pattern connection may drive
+     * multiple sinks, so the prepacker's single-fanout assumptions are lifted for it */
+    bool pack_pattern_allow_multi_fanout;
+
     int line_num; /* used to report what line number this annotation is found in architecture file */
 
     t_pin_to_pin_annotation() noexcept {
         line_num = 0;
         type = (e_pin_to_pin_annotation_type)0;
         format = (e_pin_to_pin_annotation_format)0;
+        pack_pattern_allow_multi_fanout = false;
     }
 };
 
@@ -1490,6 +1495,9 @@ class t_pb_graph_edge {
     int num_pack_patterns;
     std::vector<const char*> pack_pattern_names;
     int* pack_pattern_indices;
+    /* [0..num_pack_patterns-1] parallel to pack_pattern_names: true if the
+     * pattern annotation on this edge is marked allow_multi_fanout */
+    std::vector<bool> pack_pattern_allow_multi_fanout;
     bool infer_pattern;
 
     int switch_type_idx = ARCH_FPGA_UNDEFINED_VAL; /* architecture switch id of the edge - used when flat_routing is enabled */
@@ -1797,12 +1805,6 @@ struct t_arch_switch_inf {
     e_power_buffer_type power_buffer_type = POWER_BUFFER_TYPE_AUTO;
     float power_buffer_size = 0.;
 
-    // The template ID of the switch. This is metadata stored for each switch to
-    // simplify certain analyses. For example, when generating the CRR graph, the
-    // template ID is used to determine which switch in the template is used most
-    // or least frequently.
-    std::string template_id = "";
-
     bool intra_tile = false;
 
   public:

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -1165,6 +1165,8 @@ static void process_pin_to_pin_annotations(pugi::xml_node Parent,
         prop = get_attribute(Parent, "out_port", loc_data).value();
         annotation->output_pins = prop;
 
+        annotation->pack_pattern_allow_multi_fanout = get_attribute(Parent, "allow_multi_fanout", loc_data, ReqOpt::OPTIONAL).as_bool(false);
+
     } else {
         archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
                        vtr::string_fmt("Unknown port type %s in %s in %s",

libs/librrgraph/src/base/rr_switch.h

@@ -31,12 +31,6 @@ struct t_rr_switch_inf {
     e_power_buffer_type power_buffer_type = POWER_BUFFER_TYPE_UNDEFINED;
     float power_buffer_size = 0.;
 
-    // The template ID of the switch. This is metadata stored for each switch to
-    // simplify certain analyses. For example, when generating the CRR graph, the
-    // template ID is used to determine which switch in the template is used most
-    // or least frequently.
-    std::string template_id = "";
-
     /// Indicate whether this rr_switch is a switch type used inside clusters.
     /// These switch types are not specified in the architecture description file
     /// and are added when flat router is enabled.

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcxx.py C:/Users/OscarPC/source/repos/OpenFPGA/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: C:\Users\OscarPC\source\repos\OpenFPGA\vtr-verilog-to-routing\libs\librrgraph\src\io\rr_graph.xsd
- * md5sum of input file: f991ca82094c66d88dc58873b07cadda
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/amohaghegh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/amohaghegh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: 4b2ef78f43cba03933974d33ee053c65
  */
 
 #include <functional>
@@ -245,8 +245,8 @@ constexpr const char *atok_lookup_t_sizing[] = {"buf_size", "mux_trans_size"};
 
 enum class gtok_t_switch {TIMING, SIZING};
 constexpr const char *gtok_lookup_t_switch[] = {"timing", "sizing"};
-enum class atok_t_switch {ID, NAME, TEMPLATE_ID, TYPE};
-constexpr const char *atok_lookup_t_switch[] = {"id", "name", "template_id", "type"};
+enum class atok_t_switch {ID, NAME, TYPE};
+constexpr const char *atok_lookup_t_switch[] = {"id", "name", "type"};
 
 enum class gtok_t_switches {SWITCH};
 constexpr const char *gtok_lookup_t_switches[] = {"switch"};
@@ -672,29 +672,6 @@ inline atok_t_switch lex_attr_t_switch(const char *in, const std::function<void(
 		default: break;
 		}
 		break;
-	case 11:
-		switch(*((triehash_uu64*)&in[0])){
-		case onechar('t', 0, 64) | onechar('e', 8, 64) | onechar('m', 16, 64) | onechar('p', 24, 64) | onechar('l', 32, 64) | onechar('a', 40, 64) | onechar('t', 48, 64) | onechar('e', 56, 64):
-			switch(in[8]){
-			case onechar('_', 0, 8):
-				switch(in[9]){
-				case onechar('i', 0, 8):
-					switch(in[10]){
-					case onechar('d', 0, 8):
-						return atok_t_switch::TEMPLATE_ID;
-					break;
-					default: break;
-					}
-				break;
-				default: break;
-				}
-			break;
-			default: break;
-			}
-		break;
-		default: break;
-		}
-		break;
 	default: break;
 	}
 	noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of <switch>.").c_str());
@@ -2427,7 +2404,7 @@ inline void load_sizing_required_attributes(const pugi::xml_node &root, float *
 }
 
 inline void load_switch_required_attributes(const pugi::xml_node &root, int * id, const std::function<void(const char *)> * report_error){
-	std::bitset<4> astate = 0;
+	std::bitset<3> astate = 0;
 	for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){
 		atok_t_switch in = lex_attr_t_switch(attr.name(), report_error);
 		if(astate[(int)in] == 0) astate[(int)in] = 1;
@@ -2439,16 +2416,13 @@ inline void load_switch_required_attributes(const pugi::xml_node &root, int * id
 		case atok_t_switch::NAME:
 			/* Attribute name set after element init */
 			break;
-		case atok_t_switch::TEMPLATE_ID:
-			/* Attribute template_id set after element init */
-			break;
 		case atok_t_switch::TYPE:
 			/* Attribute type set after element init */
 			break;
 		default: break; /* Not possible. */
 		}
 	}
-	std::bitset<4> test_astate = astate | std::bitset<4>(0b1100);
+	std::bitset<3> test_astate = astate | std::bitset<3>(0b100);
 	if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_switch, report_error);
 }
 
@@ -2919,9 +2893,6 @@ inline void load_switch(const pugi::xml_node &root, T &out, Context &context, co
 		case atok_t_switch::NAME:
 			out.set_switch_name(attr.value(), context);
 			break;
-		case atok_t_switch::TEMPLATE_ID:
-			out.set_switch_template_id(attr.value(), context);
-			break;
 		case atok_t_switch::TYPE:
 			out.set_switch_type(lex_enum_switch_type(attr.value(), true, report_error), context);
 			break;
@@ -4107,8 +4078,6 @@ inline void write_switches(T &in, std::ostream &os, Context &context){
 			os << "<switch";
 			os << " id=\"" << in.get_switch_id(child_context) << "\"";
 			os << " name=\"" << in.get_switch_name(child_context) << "\"";
-			if((bool)in.get_switch_template_id(child_context))
-				os << " template_id=\"" << in.get_switch_template_id(child_context) << "\"";
 			if((bool)in.get_switch_type(child_context))
 				os << " type=\"" << lookup_switch_type[(int)in.get_switch_type(child_context)] << "\"";
 			os << ">";

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcap.py C:/Users/OscarPC/source/repos/OpenFPGA/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: C:\Users\OscarPC\source\repos\OpenFPGA\vtr-verilog-to-routing\libs\librrgraph\src\io\rr_graph.xsd
- * md5sum of input file: f991ca82094c66d88dc58873b07cadda
+ * Cmdline: uxsdcxx/uxsdcap.py /home/amohaghegh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/amohaghegh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: 4b2ef78f43cba03933974d33ee053c65
  */
 
 #include <functional>
@@ -554,7 +554,6 @@ inline void load_switch_capnp_type(const ucap::Switch::Reader &root, T &out, Con
 	(void)stack;
 
 	out.set_switch_name(root.getName().cStr(), context);
-	out.set_switch_template_id(root.getTemplateId().cStr(), context);
 	out.set_switch_type(conv_enum_switch_type(root.getType(), report_error), context);
 	stack->push_back(std::make_pair("getTiming", 0));
 	if (root.hasTiming()) {
@@ -1087,8 +1086,6 @@ inline void write_switches_capnp_type(T &in, ucap::Switches::Builder &root, Cont
 		auto child_context = in.get_switches_switch(i, context);
 		switches_switch.setId(in.get_switch_id(child_context));
 		switches_switch.setName(in.get_switch_name(child_context));
-		if((bool)in.get_switch_template_id(child_context))
-			switches_switch.setTemplateId(in.get_switch_template_id(child_context));
 		if((bool)in.get_switch_type(child_context))
 			switches_switch.setType(conv_to_enum_switch_type(in.get_switch_type(child_context)));
 		write_switch_capnp_type(in, switches_switch, child_context);

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcxx.py C:/Users/OscarPC/source/repos/OpenFPGA/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: C:\Users\OscarPC\source\repos\OpenFPGA\vtr-verilog-to-routing\libs\librrgraph\src\io\rr_graph.xsd
- * md5sum of input file: f991ca82094c66d88dc58873b07cadda
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/amohaghegh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/amohaghegh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: 4b2ef78f43cba03933974d33ee053c65
  */
 
 #include <functional>
@@ -200,14 +200,11 @@ class RrGraphBase {
 	 *   <xs:attribute name="name" type="xs:string" use="required" />
 	 *   
 	 *   <xs:attribute name="type" type="switch_type" />
-	 *   <xs:attribute name="template_id" type="xs:string" />
 	 * </xs:complexType>
 	*/
 	virtual inline int get_switch_id(typename ContextTypes::SwitchReadContext &ctx) = 0;
 	virtual inline const char * get_switch_name(typename ContextTypes::SwitchReadContext &ctx) = 0;
 	virtual inline void set_switch_name(const char * name, typename ContextTypes::SwitchWriteContext &ctx) = 0;
-	virtual inline const char * get_switch_template_id(typename ContextTypes::SwitchReadContext &ctx) = 0;
-	virtual inline void set_switch_template_id(const char * template_id, typename ContextTypes::SwitchWriteContext &ctx) = 0;
 	virtual inline enum_switch_type get_switch_type(typename ContextTypes::SwitchReadContext &ctx) = 0;
 	virtual inline void set_switch_type(enum_switch_type type, typename ContextTypes::SwitchWriteContext &ctx) = 0;
 	virtual inline typename ContextTypes::TimingWriteContext init_switch_timing(typename ContextTypes::SwitchWriteContext &ctx) = 0;