Merge branch 'master' into remove_per_layer_bb

Author: soheilshahrouz

.readthedocs.yaml

@@ -10,8 +10,11 @@ sphinx:
   builder: dirhtml
   configuration: doc/src/conf.py
 
-# Optionally build your docs in additional formats such as PDF and ePub
-formats: all
+# Build the HTML site and the downloadable PDF. Each format is a separate full
+# Sphinx run; also building htmlzip and epub pushed the build past Read the Docs'
+# time limit, so those are left off. Add them back here only if needed.
+formats:
+  - pdf
 
 # Optionally set the version of Python and requirements required to build your docs
 build:

doc/_doxygen/vpr.dox

@@ -8,6 +8,7 @@ EXTRACT_STATIC         = YES
 WARN_IF_UNDOCUMENTED   = NO
 INPUT                  = ../../vpr ../../libs/libarchfpga/
 RECURSIVE              = YES
+EXCLUDE_PATTERNS       = */test/* */tests/* */gen/*
 GENERATE_HTML          = NO
 GENERATE_LATEX         = NO
 GENERATE_XML           = YES

doc/src/mosaic/index.rst

@@ -14,9 +14,3 @@ Mosaic is a Yosys-based synthesis frontend for VTR, it is an alternative to Pamr
 Select Mosaic with ``-start mosaic`` on :ref:`run_vtr_flow`. Parmys remains the default frontend. Mosaic writes a LUT-mapped BLIF (``<circuit>.mosaic.blif``), so the flow skips the external ABC stage and continues into VPR.
 
 The default VTR build includes Mosaic (``WITH_MOSAIC``, default ``ON``). The plugin is installed at ``build/share/yosys/plugins/mosaic.so``.
-
-.. toctree::
-   :maxdepth: 2
-
-   users
-   developers

doc/src/vpr/command_line_usage.rst

@@ -862,6 +862,8 @@ For people not working on CAD, you can probably leave all the options to their d
 
     Controls the verbosity of clustering output.
     Larger values produce more detailed output, which may be useful for debugging architecture packing problems.
+    At ``2`` (the default) the clustered-netlist check prints only aggregate counts of unusual blocks (e.g. single-output blocks that may be constant generators).
+    At ``3`` or higher these blocks are also listed individually.
 
     **Default:** ``2``
 

libs/EXTERNAL/libcatch2

@@ -5,7 +5,7 @@ pandas
 numpy
 scipy
 # Python linter and formatter
-click==8.4.2
+click==8.5.0
 black==26.5.1
 pylint==4.0.7
 

requirements.txt

@@ -160,7 +160,7 @@ class APClusterPlacer {
                     const char* constraints_file)
         : place_macros_(place_macros) {
         // Initialize the block loc registry.
-        auto& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry();
+        BlkLocRegistry& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry();
         blk_loc_registry.init();
 
         // Place the fixed blocks and mark them as fixed.
@@ -188,7 +188,7 @@ class APClusterPlacer {
         const FloorplanningContext& floorplanning_ctx = g_vpr_ctx.floorplanning();
         const ClusteringContext& cluster_ctx = g_vpr_ctx.clustering();
         const auto& block_locs = g_vpr_ctx.placement().block_locs();
-        auto& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry();
+        BlkLocRegistry& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry();
         // If this block has already been placed, just return true.
         // TODO: This should be investigated further. What I think is happening
         //       is that a macro is being placed which contains another cluster.
@@ -232,7 +232,7 @@ class APClusterPlacer {
     //       centroid, then random, then exhaustive.
     bool exhaustively_place_cluster(ClusterBlockId clb_blk_id) {
         const auto& block_locs = g_vpr_ctx.placement().block_locs();
-        auto& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry();
+        BlkLocRegistry& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry();
         // If this block has already been placed, just return true.
         // TODO: See similar comment above.
         if (is_block_placed(clb_blk_id, block_locs))
@@ -343,7 +343,7 @@ FlatRecon::sort_and_group_blocks_by_tile(const PartialPlacement& p_placement) {
     for (APBlockId blk_id : ap_netlist_.blocks()) {
         t_physical_tile_loc tile_loc = p_placement.get_containing_tile_loc(blk_id);
         for (PackMoleculeId mol_id : ap_netlist_.block_molecules(blk_id)) {
-            const auto& mol = prepacker_.get_molecule(mol_id);
+            const t_pack_molecule& mol = prepacker_.get_molecule(mol_id);
 
             int num_ext_inputs = prepacker_.calc_molecule_stats(mol_id, atom_netlist_, arch_.models).num_used_ext_inputs;
             bool long_chain = mol.is_chain() && prepacker_.get_molecule_chain_info(mol.chain_id).is_long_chain;
@@ -374,7 +374,7 @@ FlatRecon::sort_and_group_blocks_by_tile(const PartialPlacement& p_placement) {
     // Group the molecules by root tile. Any non-zero offset gets
     // pulled back to its root.
     std::unordered_map<t_physical_tile_loc, std::vector<PackMoleculeId>> tile_blocks;
-    mol_desired_physical_tile_loc.reserve(prepacker_.molecules().size());
+    mol_desired_physical_tile_loc.resize(prepacker_.molecules().size());
     for (const auto& [mol_id, ext_pins, is_long_chain, tile_loc] : sorted_blocks) {
         int width_offset = device_grid_.get_width_offset(tile_loc);
         int height_offset = device_grid_.get_height_offset(tile_loc);
@@ -1366,7 +1366,7 @@ void FullLegalizer::update_drawing_data_structures() {
 }
 
 void FullLegalizer::recreate_device_if_needed() {
-    const auto& device_ctx = g_vpr_ctx.device();
+    const DeviceContext& device_ctx = g_vpr_ctx.device();
     // Capture before grid recreation: vpr_create_device_grid only writes
     // device_ctx.grid and does not touch the RR graph, so this flag remains
     // valid after the call.

vpr/src/analytical_place/full_legalization/full_legalizer.cpp

@@ -415,10 +415,16 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
 
 int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) {
     int num_undriven_pins_marked_const = mark_undriven_primitive_outputs_as_constant(netlist, verbosity);
-    VTR_LOGV(verbosity > 0, "Inferred %4d additional primitive pins as constant generators since they have no combinationally connected inputs\n", num_undriven_pins_marked_const);
+    // A primitive output with nothing feeding it can never change, so it is marked as a constant.
+    VTR_LOGV(verbosity > 0 && num_undriven_pins_marked_const > 0,
+             "Found %d primitive output pin(s) with no connected inputs; marked them as constants\n",
+             num_undriven_pins_marked_const);
 
     int num_inferred_pins_marked_const = infer_and_mark_constant_pins(netlist, const_gen_inference_method, models, verbosity);
-    VTR_LOGV(verbosity > 0, "Inferred %4d additional primitive pins as constant generators due to constant inputs\n", num_inferred_pins_marked_const);
+    // A primitive output whose inputs are all constant is itself constant.
+    VTR_LOGV(verbosity > 0 && num_inferred_pins_marked_const > 0,
+             "Found %d primitive output pin(s) driven only by constants; marked them as constants\n",
+             num_inferred_pins_marked_const);
 
     return num_undriven_pins_marked_const + num_inferred_pins_marked_const;
 }

vpr/src/base/atom_netlist_utils.cpp

@@ -33,7 +33,19 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
 
 static int check_for_duplicated_names();
 
-static int check_clb_conn(ClusterBlockId iblk, int num_conn);
+/**
+ * @brief Checks that the connections into and out of the clb make sense.
+ *
+ * A block with a single connection is flagged: an input-only block is hanging
+ * logic that should have been swept (removed before packing by iteratively
+ * deleting primitives, nets, and I/Os that have no path to a primary output),
+ * and an output-only block is likely a constant generator.
+ */
+static int check_clb_conn(ClusterBlockId iblk,
+                          int num_conn,
+                          int verbosity,
+                          int& num_input_only_blocks,
+                          int& num_output_only_blocks);
 
 static int check_clb_internal_nets(ClusterBlockId iblk, const IntraLbPbPinLookup& intra_lb_pb_pini_lookup);
 
@@ -104,16 +116,27 @@ void check_netlist(int verbosity, const t_arch& arch) {
     IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types);
 
     /* Check that each block makes sense. */
+    int num_input_only_blocks = 0;
+    int num_output_only_blocks = 0;
     for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
         num_conn = (int)cluster_ctx.clb_nlist.block_pins(blk_id).size();
-        error += check_clb_conn(blk_id, num_conn);
+        error += check_clb_conn(blk_id, num_conn, verbosity, num_input_only_blocks, num_output_only_blocks);
         error += check_clb_internal_nets(blk_id, intra_lb_pb_pin_lookup);
         if (error >= ERROR_THRESHOLD) {
             VPR_ERROR(VPR_ERROR_OTHER,
                       "Too many errors in netlist, exiting.\n");
         }
     }
 
+    VTR_LOGV(num_output_only_blocks > 0,
+             "Found %d logic block(s) with only 1 output pin and no inputs; they may be constant generators%s\n",
+             num_output_only_blocks,
+             verbosity > 2 ? "" : " (run with --pack_verbosity 3 to list them)");
+    VTR_LOGV_WARN(num_input_only_blocks > 0,
+                  "Found %d logic block(s) with only 1 input pin; the whole block is hanging logic that should be swept%s\n",
+                  num_input_only_blocks,
+                  verbosity > 2 ? "" : " (run with --pack_verbosity 3 to list them)");
+
     error += check_for_duplicated_names();
 
     error += check_external_directs_legality(arch);
@@ -162,8 +185,11 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
     return global_to_non_global_connection_count;
 }
 
-///@brief Checks that the connections into and out of the clb make sense.
-static int check_clb_conn(ClusterBlockId iblk, int num_conn) {
+static int check_clb_conn(ClusterBlockId iblk,
+                          int num_conn,
+                          int verbosity,
+                          int& num_input_only_blocks,
+                          int& num_output_only_blocks) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& clb_nlist = cluster_ctx.clb_nlist;
 
@@ -175,20 +201,22 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) {
             auto pin_type = clb_nlist.pin_type(pin_id);
 
             if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk)) {
-                //Input only and not a Primary-Output block
-                VTR_LOG_WARN(
-                    "Logic block #%d (%s) has only 1 input pin '%s'"
-                    " -- the whole block is hanging logic that should be swept.\n",
-                    iblk, clb_nlist.block_name(iblk).c_str(),
-                    clb_nlist.pin_name(pin_id).c_str());
+                // Input only and not a Primary-Output block
+                ++num_input_only_blocks;
+                VTR_LOGV_WARN(verbosity > 2,
+                              "Logic block #%d (%s) has only 1 input pin '%s'"
+                              " -- the whole block is hanging logic that should be swept.\n",
+                              iblk, clb_nlist.block_name(iblk).c_str(),
+                              clb_nlist.pin_name(pin_id).c_str());
             }
             if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk)) {
-                //Output only and not a Primary-Input block
-                VTR_LOG_WARN(
-                    "Logic block #%d (%s) has only 1 output pin '%s'."
-                    " It may be a constant generator.\n",
-                    iblk, clb_nlist.block_name(iblk).c_str(),
-                    clb_nlist.pin_name(pin_id).c_str());
+                // Output only and not a Primary-Input block
+                ++num_output_only_blocks;
+                VTR_LOGV(verbosity > 2,
+                         "Logic block #%d (%s) has only 1 output pin '%s'."
+                         " It may be a constant generator.\n",
+                         iblk, clb_nlist.block_name(iblk).c_str(),
+                         clb_nlist.pin_name(pin_id).c_str());
             }
 
             break;

vpr/src/base/check_netlist.cpp

@@ -92,8 +92,10 @@ static void sync_clustered_and_atom_netlists(ClusteredNetlist& clb_nlist,
 /**
  * @brief This function updates the nets list and the connections between
  *        that list and the complex block
+ *
+ * A net that reaches both global and non-global pins is flagged with a warning.
  */
-static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist, const AtomNetlist& atom_netlist);
+static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist, const AtomNetlist& atom_netlist, int verbosity);
 
 static void load_internal_to_block_net_nums(const t_logical_block_type_ptr type, t_pb_routes& pb_route);
 
@@ -270,7 +272,7 @@ ClusteredNetlist read_netlist(const char* net_file,
 
         mark_constant_generators(clb_nlist, verbosity);
 
-        load_external_nets_and_cb(clb_nlist, mutable_atom_netlist);
+        load_external_nets_and_cb(clb_nlist, mutable_atom_netlist, verbosity);
 
         sync_clustered_and_atom_netlists(clb_nlist, mutable_atom_netlist, mutable_atom_lookup);
 
@@ -889,7 +891,8 @@ static void process_ports(pugi::xml_node Parent,
 }
 
 static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist,
-                                      const AtomNetlist& atom_netlist) {
+                                      const AtomNetlist& atom_netlist,
+                                      int verbosity) {
     // Create a set of all unique net names that we can see. We want to ignore
     // any nets with the name "open", so we insert that into the map and later
     // we just ignore it if it was seen,
@@ -1035,21 +1038,33 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist,
     // set, minus the "open" nets.
     int num_unique_net_names = seen_net_names.size() - 1;
     VTR_ASSERT(static_cast<int>(clb_nlist.nets().size()) == num_unique_net_names);
+    int num_mixed_global_nets = 0;
     for (ClusterNetId net_id : clb_nlist.nets()) {
+        bool is_ignored_net = clb_nlist.net_is_ignored(net_id);
         for (ClusterPinId pin_id : clb_nlist.net_sinks(net_id)) {
-            bool is_ignored_net = clb_nlist.net_is_ignored(net_id);
             t_logical_block_type_ptr block_type = clb_nlist.block_type(clb_nlist.pin_block(pin_id));
             t_physical_tile_type_ptr tile_type = pick_physical_type(block_type);
             int logical_pin = clb_nlist.pin_logical_index(pin_id);
             int physical_pin = get_physical_pin(tile_type, block_type, logical_pin);
 
             if (tile_type->is_ignored_pin[physical_pin] != is_ignored_net) {
-                VTR_LOG_WARN(
-                    "Netlist connects net %s to both global and non-global pins.\n",
-                    clb_nlist.net_name(net_id).c_str());
+                ++num_mixed_global_nets;
+                // The net reaches an ignored (global) pin, so the whole net is
+                // treated as global and left unrouted; its non-global sinks get
+                // ideal (zero) delay instead of a routed connection.
+                VTR_LOGV_WARN(verbosity > 2,
+                              "Net '%s' connects both routed pins and ignored (global) pins; it will be treated as global and left unrouted, with ideal delay on its non-global sinks.\n",
+                              clb_nlist.net_name(net_id).c_str());
+                break;
             }
         }
     }
+
+    VTR_LOGV_WARN(num_mixed_global_nets > 0,
+                  "Found %d net(s) mixing routed and ignored pins; these are left unrouted with ideal delay. "
+                  "This is expected for clock nets under --clock_modeling ideal; use --clock_modeling route or dedicated_network to route them.%s\n",
+                  num_mixed_global_nets,
+                  verbosity > 2 ? "" : " (run with --pack_verbosity 3 to list the nets)");
 }
 
 static void mark_constant_generators(const ClusteredNetlist& clb_nlist, int verbosity) {