Add br_amba_axil2apb test (#1213)

Add simulation coverage for `br_amba_axil2apb` and refactor shared AMBA
simulation helpers so AXI-Lite/APB drivers and monitors can be reused
across benches.
- Add `br_amba_axil2apb_tb` with directed and randomized scenarios for:
  - reset/idle behavior
  - no-delay reads and writes
  - zero-strobe writes
  - APB `PREADY` backpressure on reads and writes
  - independent AW/W channel skew
  - read/write arbitration
  - AXI B/R response backpressure
  - APB `PSLVERR` propagation
  - mixed directed traffic
  - sustained stress traffic
  - mid-transaction reset recovery

- Add `br_amba_axil2apb_scoreboard` to predict protocol-agnostic
transactions from AXI-Lite observations and verify:
  - AXI-Lite request payloads
  - APB transfer payloads and timing
  - AXI-Lite response payloads and timing
  - read/write arbitration priority

- Add/refactor reusable simulation components:
  - generic AXI-Lite requester driver
- generic AXI-Lite monitor with channel observations and protocol checks
  - generic APB monitor with request/completion timestamps
  - APB completer response queue support
  - shared AMBA sim helpers and protocol transaction types

- Rename the existing AXI-Lite driver to `br_amba_axil_completer_driver`
to clarify side ownership.
- Update AXI-Lite default target tests to use the common helper
structure.

Depends on: #1183 and
#1197.

---------

Co-authored-by: Wiktoria Kuna <wkuna@antmicro.com>

Author: mczyz-antmicro

amba/sim/BUILD.bazel

@@ -4,6 +4,88 @@ load("@rules_hdl//verilog:providers.bzl", "verilog_library")
 load("//bazel:br_verilog.bzl", "br_verilog_sim_test_tools_suite")
 load("//bazel:verilog.bzl", "verilog_elab_test")
 
+BR_AMBA_SIM_MAX_CHECK_WIDTH_64 = "BR_AMBA_SIM_MAX_CHECK_WIDTH=64"
+
+BR_AMBA_SIM_DEFINES_64 = [
+    "BR_ASSERT_ON",
+    "BR_ENABLE_IMPL_CHECKS",
+    "SIMULATION",
+    BR_AMBA_SIM_MAX_CHECK_WIDTH_64,
+]
+
+BR_AMBA_APB_TIMING_SLICE_DEFINES = [
+    "BR_AMBA_APB_SIM_ADDR_WIDTH=32",
+    "BR_AMBA_APB_SIM_DATA_WIDTH=32",
+]
+
+verilog_library(
+    name = "br_amba_axil2apb_sim_pkg",
+    srcs = ["br_amba_axil2apb_sim_pkg.sv"],
+    visibility = ["//visibility:public"],
+    deps = [
+        "//amba/rtl:br_amba_pkg",
+        "//amba/sim/drivers:br_amba_apb_sim_pkg",
+    ],
+)
+
+verilog_library(
+    name = "br_amba_axil2apb_tb",
+    srcs = ["br_amba_axil2apb_tb.sv"],
+    deps = [
+        ":br_amba_axil2apb_sim_pkg",
+        "//amba/rtl:br_amba_axil2apb",
+        "//amba/sim/drivers:br_amba_apb_sim_helpers",
+        "//amba/sim/drivers:br_amba_axil_requester_driver",
+        "//amba/sim/drivers:br_amba_sim_pkg",
+        "//amba/sim/monitors:br_amba_apb_monitor",
+        "//amba/sim/monitors:br_amba_axil2apb_scoreboard",
+        "//amba/sim/monitors:br_amba_axil_monitor",
+        "//amba/sim/monitors:br_amba_axil_monitor_sim_pkg",
+        "//macros:br_asserts",
+        "//misc/sim:br_test_driver",
+    ],
+)
+
+verilog_elab_test(
+    name = "br_amba_axil2apb_tb_elab_test",
+    defines = [
+        "BR_AMBA_SIM_MAX_CHECK_WIDTH=32",
+        "BR_AMBA_AXIL_SIM_ADDR_WIDTH=12",
+        "BR_AMBA_AXIL_SIM_DATA_WIDTH=32",
+        "BR_AMBA_AXIL_SIM_USER_WIDTH=1",
+        "BR_AMBA_APB_SIM_ADDR_WIDTH=12",
+        "BR_AMBA_APB_SIM_DATA_WIDTH=32",
+    ],
+    tool = "slang",
+    deps = [":br_amba_axil2apb_tb"],
+)
+
+[
+    br_verilog_sim_test_tools_suite(
+        name = "br_amba_axil2apb_sim_test_tools_suite_dw%s" % data_width,
+        defines = [
+            "BR_ASSERT_ON",
+            "BR_ENABLE_IMPL_CHECKS",
+            "SIMULATION",
+            "BR_AMBA_SIM_MAX_CHECK_WIDTH=%s" % data_width,
+            "BR_AMBA_AXIL_SIM_ADDR_WIDTH=12",
+            "BR_AMBA_AXIL_SIM_DATA_WIDTH=%s" % data_width,
+            "BR_AMBA_AXIL_SIM_USER_WIDTH=1",
+            "BR_AMBA_APB_SIM_ADDR_WIDTH=12",
+            "BR_AMBA_APB_SIM_DATA_WIDTH=%s" % data_width,
+        ],
+        tools = [
+            "vcs",
+            "verilator",
+        ],
+        deps = [":br_amba_axil2apb_tb"],
+    )
+    for data_width in [
+        "32",
+        "64",
+    ]
+]
+
 verilog_library(
     name = "br_amba_apb_timing_slice_tb",
     srcs = ["br_amba_apb_timing_slice_tb.sv"],
@@ -17,12 +99,14 @@ verilog_library(
 
 verilog_elab_test(
     name = "br_amba_apb_timing_slice_tb_elab_test",
+    defines = BR_AMBA_APB_TIMING_SLICE_DEFINES,
     tool = "slang",
     deps = [":br_amba_apb_timing_slice_tb"],
 )
 
 br_verilog_sim_test_tools_suite(
     name = "br_amba_apb_timing_slice_sim_test_tools_suite",
+    defines = BR_AMBA_APB_TIMING_SLICE_DEFINES,
     params = {
         "AddrWidth": [
             "12",
@@ -176,6 +260,9 @@ verilog_elab_test(
         "BR_AMBA_AXI_SIM_DATA_WIDTH=32",
         "BR_AMBA_AXI_SIM_ID_WIDTH=3",
         "BR_AMBA_AXI_SIM_USER_WIDTH=2",
+        "BR_AMBA_AXIL_SIM_ADDR_WIDTH=12",
+        "BR_AMBA_AXIL_SIM_DATA_WIDTH=32",
+        "BR_AMBA_AXIL_SIM_USER_WIDTH=2",
     ],
     tool = "slang",
     deps = [":br_amba_axi2axil_tb"],
@@ -192,6 +279,9 @@ verilog_elab_test(
             "BR_AMBA_AXI_SIM_DATA_WIDTH=%s" % data_width,
             "BR_AMBA_AXI_SIM_ID_WIDTH=3",
             "BR_AMBA_AXI_SIM_USER_WIDTH=2",
+            "BR_AMBA_AXIL_SIM_ADDR_WIDTH=12",
+            "BR_AMBA_AXIL_SIM_DATA_WIDTH=%s" % data_width,
+            "BR_AMBA_AXIL_SIM_USER_WIDTH=2",
         ],
         params = {
             "MaxOutstandingReqs": [
@@ -356,7 +446,8 @@ verilog_library(
     srcs = ["br_amba_axil_default_target_tb.sv"],
     deps = [
         "//amba/rtl:br_amba_axil_default_target",
-        "//amba/sim/drivers:br_amba_axil_driver",
+        "//amba/sim/drivers:br_amba_axil_completer_driver",
+        "//amba/sim/drivers:br_amba_sim_pkg",
         "//amba/sim/monitors:br_amba_axil_monitor",
         "//misc/sim:br_test_driver",
     ],
@@ -392,3 +483,46 @@ br_verilog_sim_test_tools_suite(
     ],
     deps = [":br_amba_axil_default_target_tb"],
 )
+
+verilog_library(
+    name = "br_amba_atb_funnel_tb",
+    srcs = ["br_amba_atb_funnel_tb.sv"],
+    deps = [
+        "//amba/rtl:br_amba_atb_funnel",
+        "//misc/sim:br_test_driver",
+    ],
+)
+
+verilog_elab_test(
+    name = "br_amba_atb_funnel_tb_elab_test",
+    tool = "slang",
+    deps = [":br_amba_atb_funnel_tb"],
+)
+
+br_verilog_sim_test_tools_suite(
+    name = "br_amba_atb_funnel_sim_test_tools_suite",
+    params = {
+        "DataWidth": [
+            "32",
+            "64",
+        ],
+        "NumSources": [
+            "2",
+            "4",
+            "17",
+        ],
+        "RegisterAtReady": [
+            "0",
+            "1",
+        ],
+        "UserWidth": [
+            "1",
+            "3",
+        ],
+    },
+    tools = [
+        "vcs",
+        "verilator",
+    ],
+    deps = [":br_amba_atb_funnel_tb"],
+)

amba/sim/br_amba_apb_timing_slice_tb.sv

@@ -61,11 +61,11 @@ module br_amba_apb_timing_slice_tb;
   function automatic apb_request_t get_request(
       input logic [AddrWidth-1:0] addr, input logic [ApbProtWidth-1:0] prot, input logic [3:0] strb,
       input logic write, input logic [31:0] wdata);
-    get_request.addr  = addr;
+    get_request.addr  = ApbAddrWidth'(addr);
     get_request.prot  = prot;
-    get_request.strb  = strb;
+    get_request.strb  = ApbStrbWidth'(strb);
     get_request.write = write;
-    get_request.wdata = wdata;
+    get_request.wdata = ApbDataWidth'(wdata);
   endfunction
 
   function automatic apb_request_controls_t get_request_controls(
@@ -77,7 +77,7 @@ module br_amba_apb_timing_slice_tb;
 
   function automatic apb_response_t get_response(input logic [31:0] rdata, input logic slverr);
     get_response.ready  = 1'b1;
-    get_response.rdata  = rdata;
+    get_response.rdata  = ApbDataWidth'(rdata);
     get_response.slverr = slverr;
   endfunction
 
@@ -89,6 +89,7 @@ module br_amba_apb_timing_slice_tb;
 
   logic monitor_enable;
   logic monitor_done;
+  logic completer_failed;
 
   br_amba_apb_timing_slice #(
       .AddrWidth(AddrWidth)
@@ -147,7 +148,8 @@ module br_amba_apb_timing_slice_tb;
       .target_penable(penable_out),
       .pready(pready_in),
       .prdata(prdata_in),
-      .pslverr(pslverr_in)
+      .pslverr(pslverr_in),
+      .failed(completer_failed)
   );
 
   br_amba_apb_timing_slice_monitor #(
@@ -183,7 +185,7 @@ module br_amba_apb_timing_slice_tb;
       input apb_request_t request, input apb_request_controls_t request_controls,
       input apb_response_t response, input apb_response_controls_t response_controls);
     for (int transaction = 0; transaction < response_controls.num_transactions; transaction++) begin
-      monitor.expect_response(response.rdata + 32'(transaction), response.slverr);
+      monitor.expect_response(32'(response.rdata) + 32'(transaction), response.slverr);
     end
     fork
       requester.run(request, request_controls);
@@ -281,6 +283,7 @@ module br_amba_apb_timing_slice_tb;
 
     td.check(monitor.pending_count() == 0, "monitor response queue not empty");
     td.check(monitor.get_error_count() == 0, "APB monitor reported errors");
+    td.check(!completer_failed, "APB completer reported failures");
     monitor_enable = 1'b0;
     monitor_done   = 1'b1;
     td.finish();