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samples: net: dsa: Add KSZ8463MLI net shell sample
Provide a sample showing how the KSZ8463 is configured for the Cortex-M7 CPU on ST's Nucleo H755ZI-Q. The KSZ8463MLI evaluation board is assumed to be connected to spi1. The primary focus of the sample is illustrating a proper devicetree configuration. The software included does nothing. Instead, users are expected to use the net shell to manage the DSA interfaces. Signed-off-by: Vilhelm Engström <vilhelm.engstrom@tuta.io>
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‎samples/net/ethernet/dsa_ksz8463ml/CMakeLists.txt‎

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# Copyright (c) 2026 Vilhelm Engström
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#
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(dsa_ksz8463)
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target_sources(app PRIVATE src/main.c)

‎samples/net/ethernet/dsa_ksz8463ml/README.rst‎

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.. zephyr:code-sample:: dsa_ksz8463ml
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:name: KSZ8463ML DSA sample
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:relevant-api: dsa_core
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Configure the KSZ8463ML evaluation board and use net-shell to view the interfaces.
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Overview
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********
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A sample application configuring the Microchip KSZ8463ML MII-based 3-port Ethernet
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switch. The sample enables the net-shell, allowing users to view and manage the DSA
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interfaces.
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Source code for the sample is available at
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:zephyr_file:`samples/net/ethernet/dsa_ksz8463ml`
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Requirements
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************
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- :ref:`networking_with_host`
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Building and Running
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********************
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The sample is built by running the following:
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.. zephyr-app-commands::
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:zephyr-app: samples/net/ethernet/dsa_ksz8463ml
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:board: <board to use>
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:conf: prj.conf
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:goals: build
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:compact:
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Using the Nucleo H755ZI-Q With the KSZ8463ML Evaluation Board
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=============================================================
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The KSZ8463ML evaluation board uses a MII connector for connecting the MAC of port 3
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--- i.e. the host/CPU port --- to an external MAC. Using the evaluation board with
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the STM32 Nucleo H755ZI-Q, which comes with an integrated LAN8742A PHY connected via
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RMII, can therefore be done in one of two ways.
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#. Desolder the LAN8742A PHY from the Nucleo board and connect the respective MII lines
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from the KSZ8463 directly to the extension connectors/through holes on the former
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#. Hook the KSZ8463ML evaluation board up to an external PHY and connect said PHY
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to the Nucleo board via Ethernet (untested).
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Note that the strap-in configuration differs between the two options. See Section 3.1.1
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in the KSZ8463ML/RL user guide.

‎samples/net/ethernet/dsa_ksz8463ml/boards/nucleo_h755zi_q_stm32h755xx_m7.overlay‎

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/*
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* Copyright (c) 2026 Vilhelm Engström
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h755zitx-pinctrl.dtsi>
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#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
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#include <zephyr/dt-bindings/ethernet/dsa_tag_proto.h>
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&mac {
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pinctrl-0 = <
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&eth_mii_col_pa3
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&eth_mii_crs_pa0
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&eth_mii_rx_clk_pa1
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&eth_mii_rx_dv_pa7
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&eth_mii_rx_er_pb10
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&eth_mii_rxd0_pc4
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&eth_mii_rxd1_pc5
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&eth_mii_rxd2_pb0
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&eth_mii_rxd3_pb1
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&eth_mii_tx_clk_pc3
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&eth_mii_tx_en_pb11
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&eth_mii_txd0_pb12
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&eth_mii_txd1_pb13
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&eth_mii_txd2_pc2
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&eth_mii_txd3_pb8
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&eth_mii_tx_er_pb2
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>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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/* KSZ8463ML uses MII */
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phy-connection-type = "mii";
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status = "okay";
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};
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&mdio {
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pinctrl-0 = <
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&eth_mdc_pc1
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&eth_mdio_pa2
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>;
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pinctrl-names = "default";
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status = "okay";
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/* PHY for CPU port */
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phy0: ethernet-phy@0 {
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/* Know the capabilities of both the MAC transceiver and
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* the switch, no sense attempting to negotiate speeds
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*/
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compatible = "ethernet-phy-fixed-link";
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/* KSZ8463 capped at 100Mbps, Full-Duplex */
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default-speeds = "100BASE Full-Duplex";
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reg = <0>;
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status = "okay";
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};
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};
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&pinctrl {
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eth_mdc_pc1: eth_mdc_pc1 {
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pinmux = <
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STM32_PINMUX('C', 1, AF11) /* ETH_MDC */
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>;
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};
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eth_mdio_pa2: eth_mdio_pa2 {
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pinmux = <
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STM32_PINMUX('A', 2, AF11) /* ETH_MDIO */
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>;
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};
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eth_mii_col_pa3: eth_mii_col_pa3 {
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pinmux = <
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STM32_PINMUX('A', 3, AF11) /* ETH_MII_COL */
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>;
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};
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eth_mii_crs_pa0: eth_mii_crs_pa0 {
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pinmux = <
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STM32_PINMUX('A', 0, AF11) /* ETH_MII_CRS */
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>;
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};
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eth_mii_rx_clk_pa1: eth_mii_rx_clk_pa1 {
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pinmux = <
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STM32_PINMUX('A', 1, AF11) /* ETH_MII_RX_CLK */
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>;
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};
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eth_mii_rx_dv_pa7: eth_mii_rx_dv_pa7 {
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pinmux = <
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STM32_PINMUX('A', 7, AF11) /* ETH_MII_RX_DV */
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>;
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};
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eth_mii_rx_er_pb10: eth_mii_rx_er_pb10 {
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pinmux = <
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STM32_PINMUX('B', 10, AF11) /* ETH_MII_RX_ER */
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>;
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};
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eth_mii_rxd0_pc4: eth_mii_rxd0_pc4 {
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pinmux = <
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STM32_PINMUX('C', 4, AF11) /* ETH_MII_RXD0 */
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>;
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};
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eth_mii_rxd1_pc5: eth_mii_rxd1_pc5 {
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pinmux = <
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STM32_PINMUX('C', 5, AF11) /* ETH_MII_RXD1 */
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>;
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};
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eth_mii_rxd2_pb0: eth_mii_rxd2_pb0 {
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pinmux = <
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STM32_PINMUX('B', 0, AF11) /* ETH_MII_RXD2 */
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>;
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};
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eth_mii_rxd3_pb1: eth_mii_rxd3_pb1 {
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pinmux = <
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STM32_PINMUX('B', 1, AF11) /* ETH_MII_RXD3 */
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>;
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};
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eth_mii_tx_clk_pc3: eth_mii_tx_clk_pc3 {
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pinmux = <
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STM32_PINMUX('C', 3, AF11) /* ETH_MII_TX_CLK */
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>;
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};
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eth_mii_tx_en_pb11: eth_mii_tx_en_pb11 {
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pinmux = <
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STM32_PINMUX('B', 11, AF11) /* ETH_MII_TX_EN */
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>;
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};
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eth_mii_tx_er_pb2: eth_mii_tx_er_pb2 {
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pinmux = <
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STM32_PINMUX('B', 2, AF11) /* ETH_TX_ER */
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>;
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};
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eth_mii_txd0_pb12: eth_mii_txd0_pb12 {
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pinmux = <
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STM32_PINMUX('B', 12, AF11) /* ETH_MII_TXD0 */
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>;
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};
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eth_mii_txd1_pb13: eth_mii_txd1_pb13 {
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pinmux = <
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STM32_PINMUX('B', 13, AF11) /* ETH_MII_TXD1 */
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>;
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};
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eth_mii_txd2_pc2: eth_mii_txd2_pc2 {
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pinmux = <
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STM32_PINMUX('C', 2, AF11) /* ETH_MII_TXD2 */
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>;
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};
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eth_mii_txd3_pb8: eth_mii_txd3_pb8 {
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pinmux = <
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STM32_PINMUX('B', 8, AF11) /* ETH_MII_TXD3 */
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>;
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};
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spi1_nss_pa4: spi1_nss_pa4 {
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pinmux = <
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STM32_PINMUX('A', 4, AF5) /* SPI1_NSS */
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>;
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};
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spi1_sck_pa5: spi1_sck_pa5 {
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pinmux = <
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STM32_PINMUX('A', 5, AF5) /* SPI1_SCK */
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>;
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};
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spi1_miso_pa6: spi1_miso_pa6 {
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pinmux = <
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STM32_PINMUX('A', 6, AF5) /* SPI1_MISO */
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>;
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};
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spi1_mosi_pa7: spi1_mosi_pa7 {
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pinmux = <
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STM32_PINMUX('A', 7, AF5) /* SPI1_MOSI */
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>;
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};
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sw1_rst_pb3: sw1_rst_pb3 {
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pinmux = <
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STM32_PINMUX('B', 3, GPIO) /* GPIO */
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>;
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};
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sw1_irq_pb5: sw1_irq_pb5 {
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pinmux = <
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STM32_PINMUX('B', 5, GPIO) /* GPIO */
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>;
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};
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};
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/* For sys_rand_get */
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&rng {
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status = "okay";
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};
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/* Switch connected to SPI bus 1 */
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&spi1 {
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cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <
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&spi1_nss_pa4
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&spi1_sck_pa5
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&spi1_miso_pa6
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&spi1_mosi_pa7
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>;
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pinctrl-names = "default";
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status = "okay";
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sw1: ethernet-switch@0 {
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compatible = "microchip,ksz8463";
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/* Chip-select 0 */
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <DT_FREQ_K(12500)>;
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/* Hardware reset is active low */
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reset-gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
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/* Interrupt output is active low */
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int-gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
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/* Enable IGMP snooping */
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microchip,igmp-snoop-en;
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/* Enable MLD snooping */
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microchip,mld-snoop-en;
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status = "okay";
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/* User port 1 */
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sw1_port1: port@0 {
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compatible = "zephyr,dsa-port";
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reg = <0>;
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/* Use random MAC */
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zephyr,random-mac-address;
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status = "okay";
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/* Internal PHY */
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phy {
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compatible = "microchip,ksz8463-phy";
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/* Fall back on 10BASE Half-Duplex on auto-negotiation failure */
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microchip,fixed-link-speed = "10BASE Half-Duplex";
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status = "okay";
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};
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};
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/* User port 2 */
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sw1_port2: port@1 {
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compatible = "zephyr,dsa-port";
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reg = <1>;
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zephyr,random-mac-address;
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status = "okay";
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/* Internal PHY */
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phy {
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compatible = "microchip,ksz8463-phy";
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/* Fall back on 100BASE Full-Duplex on auto-negotiation failure */
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microchip,fixed-link-speed = "100BASE Full-Duplex";
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status = "okay";
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};
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};
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/* CPU port */
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sw1_port3: port@2 {
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compatible = "zephyr,dsa-port";
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reg = <2>;
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/* Port is connected to the STM MAC */
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ethernet = <&mac>;
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/* KSZ8463ML uses MII */
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phy-connection-type = "mii";
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/* Enable tail tagging */
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dsa-tag-protocol = <DSA_TAG_PROTO_KSZ8463>;
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status = "okay";
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};
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};
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};

‎samples/net/ethernet/dsa_ksz8463ml/prj.conf‎

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CONFIG_NETWORKING=y
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CONFIG_NET_DSA=y
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CONFIG_SPI=y
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CONFIG_SHELL=y
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CONFIG_NET_SHELL=y
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# The KSZ8463 driver is automatically enabled whenever a node with compatible microchip,ksz8463 and
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# status okay is found in the dts.

‎samples/net/ethernet/dsa_ksz8463ml/src/main.c‎

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/*
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* Copyright (c) 2026 Vilhelm Engström
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ksz8463ml_sample, LOG_LEVEL_DBG);
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int main(void)
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{
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LOG_INF("Run 'net iface' in the shell to view the interfaces");
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return 0;
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}

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