Flash clock initialization is done at the wrong time in some bflb socs

[VynDragon]

Describe the bug

updating the flash clock is done after configuring clocks in clock control drivers, this causes a crash due to XIP loss in some setups.
This is now a possible issue because relocation of the clock control was atomized.

Regression

• This is a regression.

Steps to reproduce

• build hello_world with CONFIG_FLASH=n for TG-01M / TG7100C
• The default flash configuration is PLL and not XCLK unlike most, this triggers the issue as PLL is stopped before the clock has been switched to BCLK
• No log

Relevant log output

<no log>

Impact

Functional Limitation – Some features not working as expected, but system usable.

Environment

• linux
• zephyr sdk1.0.1
• mainline latest

Additional Context

BL616CL clock_control has this issue mostly solved, here is an example patch for bl60x

issue_was_not_fixed.patch