MSc student in Electronic Engineering at Politecnico di Torino with a focus on Digital IC Design, RTL Development, Computer Architecture, and Low-Power Digital Systems.
- Digital IC Design
- RTL Development
- Computer Architecture
- RISC-V Systems
- FPGA Prototyping
- Low-Power Digital Design
- ASIC Design Flows
- HDLs: VHDL, Verilog, SystemVerilog
- EDA Tools: Synopsys Design Compiler, Quartus, ModelSim
- Low-Power Design: UPF, Clock Gating, Power Analysis
- Programming & Scripting: C/C++, Bash, Tcl
- Pipelined FFT Butterfly Architecture
- FMC Burst-Capable Slave Interface
- Low-Power RTL Design
- RISC-V FPGA Badge
- RISC-V FPGA Badge (SemiTO-V)
- MSc studies in Electronic Engineering
- RTL Design and Digital Systems Architecture