A technical walkthrough for reviving obsolete USBasp programmers. This guide utilizes a secondary "Working" programmer to deploy modernized firmware via the In-System Programming (ISP) protocol, resolving modern avrdude compatibility bottlenecks.
Most commercial USBasp clones ship with 2008-era firmware. This results in the infamous "Warning: cannot set sck period" error because the legacy code lacks a software-controlled SCK (Serial Clock) scaler.
Updating to the 2011-05-28 stable release enables:
- Dynamic SCK Scaling: Automatic adjustment for low-speed target MCUs.
- TPI Support: Ability to program ATTiny4/5/9/10 series chips.
- Extended Compatibility: Full support for Arduino IDE 2.x and modern AVR toolchains.
To unlock the flash memory on the Target USBasp, you must short Jumper 2 (JP2). This pulls the Target's Reset line into the ISP header, allowing the Master programmer to initiate the SPI handshake.
Connect the Master and Target units via a 10-pin ribbon cable. The Master unit must be connected to the PC via USB, providing both data and VCC (5V) to the Target board.
Configure the AVRDUDESS interface with the following parameters to ensure high signal integrity:
| Register / Parameter | Target Value | Role |
|---|---|---|
| Programmer | usbasp |
Active Master Driver |
| MCU | ATmega8 |
Target Silicon |
| BitClock | 375 kHz |
Synchronous Clock Speed |
| L-Fuse | 0xEF |
Internal RC Oscillator Config |
| H-Fuse | 0xC9 |
SPI Programming Enable |
- Verification: Click "Read" in the Flash section to backup the existing firmware (Safety Check).
- Flash: Load
usbasp.atmega8.2011-05-28.hex. - Commit: Click "Write". The GUI will execute the
avrdudecommand string and verify the checksum. - Hardware Reset: Disconnect both units and remove the JP2 jumper to exit programming mode.
If the "Read" fails, verify the following:
- Common Ground: Ensure both boards share a ground via the ribbon cable.
- Driver: Ensure the libusb-win32 driver is installed via Zadig; otherwise, AVRDUDESS cannot claim the USB interface.
- BitClock: If 375 kHz fails, drop the BitClock to 32 kHz to account for chips running on default 1MHz internal clocks.
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