UART (Universal Asynchronous Receiver Transmitter) transmitter designed using Verilog HDL.
- Serial data transmission
- Start and stop bit generation
- Busy flag indication
- 8-bit data transfer
- Testbench verification using Xilinx ISim
- Finite State Machine (FSM)
- Shift operations
- Serial communication
- Sequential logic
- Timing and synchronization
- Verilog HDL
- Xilinx ISE / ISim
The UART transmitter was verified using waveform simulation and testbench analysis in ISim.