Electronics and Communication Engineering student interested in Embedded electronics, RTL Design, Verilog HDL, FPGA Design, Digital Systems and Machine Learning
- Kerala
- in/muhammed-afsal-89398431b
Pinned Loading
-
aes-128-fpga-project
aes-128-fpga-project PublicAES-128 Encryption Accelerator on Zybo Z7-10 (Zynq-7000 SoC) using Vivado and Vitis
Verilog
-
cusat-asic-fpga-design-to-deploy
cusat-asic-fpga-design-to-deploy PublicLab reports, certificate, and curriculum details from the CUSAT ASIC & FPGA SoC Design Training Program (June 2026)
-
-
FIFO-memory-module
FIFO-memory-module PublicDesigned FIFO memory module with read/write operations and status flags.
Verilog
-
UART-Transmittor
UART-Transmittor PublicDesigned UART transmitter for serial communication using Verilog HDL.
Verilog
-
Traffic-Light-Controller-using-FSM
Traffic-Light-Controller-using-FSM PublicBuilt FSM-based traffic light controller with automatic state transitions.
Verilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.