FIFO Project

Synchronous FIFO (First In First Out) buffer implemented using Verilog HDL.

Features

• 8-bit data width
• FIFO read and write operations
• Full and empty flag generation
• Underflow and overflow detection
• Testbench verification using Xilinx ISim

Concepts Used

• Sequential logic
• Registers
• Memory handling
• Pointer management
• Verification and waveform analysis

Tools Used

• Verilog HDL
• Xilinx ISE / ISim

Verification

The FIFO design was verified using a Verilog testbench and waveform simulation in ISim.

Simulation Output