fifo_tb.v

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:38:33 05/07/2026
// Design Name:   fifo
// Module Name:   /home/ise/Documents/verilog/fifo/fifo_tb.v
// Project Name:  fifo
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: fifo
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module fifo_tb;

	// Inputs
	reg clk;
	reg rst;
	reg write;
	reg read;
	reg [7:0] data_in;

	// Outputs
	wire [7:0] data_out;
	wire full;
	wire empty;

	// Instantiate the Unit Under Test (UUT)
	fifo uut (
		.clk(clk), 
		.rst(rst), 
		.write(write), 
		.read(read), 
		.data_in(data_in), 
		.data_out(data_out), 
		.full(full), 
		.empty(empty)
	);
//clock generation
always #5 clk=~clk;
initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		write = 0;
		read = 0;
		#10;
		rst = 0;
		
		$display("Starting FIFO test...");

		// Write data
		write=1;
		
		data_in=8'd10;
		#10;
		
		data_in=8'd20;
		#10;
		
		data_in=8'd30;
		#10;
		
		write=0;
        
		// read data
		
		read=1;
		
		#10;
		#10;
		#10;
		
		read=0;
		
		$display("FIFO Test Completed");
		$finish;

	end
	
	initial begin
	
	$monitor("Time=%0t | write=%b read=%b data_in=%d data_out=%d full=%b empty=%b",
	$time, write, read, data_in, data_out, full, empty);
	end
      
endmodule