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GW5A. Enable more CLKDIV2/CLKDIV #498

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Merged
yrabbit merged 1 commit into from
Apr 9, 2026
Merged

GW5A. Enable more CLKDIV2/CLKDIV #498

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28 changes: 20 additions & 8 deletions apycula/chipdb.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1082,8 +1082,10 @@ def mk_hclk_pip(hclk_idx, row, col, src, dest, fuses = set()):
dev.hclk_pips.setdefault((row, col), {}).setdefault(dest, {}).update({src: fuses})
add_node(dev, f"HCLK{hclk_idx}_{src}", "HCLK", row, col, src)
add_node(dev, dest, "GLOBAL_CLK", row, col, dest)
elif srcid in {84, 85}:
# XXX unknown CLKDIV2 inputs, skip for now
continue
if destid < hclk_off:
elif destid < hclk_off:
# skip HCLK->GCLK gates
if srcid in {28, 25, 29, 27} and destid in range(169, 185):
continue
Expand Down Expand Up @@ -1139,6 +1141,14 @@ def mk_hclk_pip(hclk_idx, row, col, src, dest, fuses = set()):
dest = f'HCLK_BUF_BI{hclk_idx}{j}'
mk_hclk_pip(hclk_idx, row, col, src, dest)

# make CLKDIV2 inputs
src = f'HCLK_BUF_BO{hclk_idx}{j}'
dest = f'CLKDIV2_I{hclk_idx}{j}'
mk_hclk_pip(hclk_idx, row, col, src, dest)
src = f'CLKDIV2_I{hclk_idx}{j}'
dest = f'HCLK_MUX_ALPHA{hclk_idx}{j}'
mk_hclk_pip(hclk_idx, row, col, src, dest)

# make default pip for inter-hclk output
src = f'HCLK_FROM_IHCLK{hclk_idx}{j}'
dest = f'HCLK_MUX_DELTA{hclk_idx}{j}'
Expand Down Expand Up @@ -1334,9 +1344,6 @@ def gw5_add_hclk_bels(dat, dev, device):
extra_clkdiv2['hclk_idx'] = hclk_idx
extra_clkdiv['hclk_idx'] = hclk_idx
for i in range(4):
# XXX skip for now
if i in {1, 3}:
continue
# CLKDIV2
dev.hclk_div2.setdefault(hclk_idx, set()).add((row, col, i))
clkdiv2 = extra_clkdiv2.setdefault('bels', {}).setdefault(i, {})
Expand All @@ -1346,10 +1353,15 @@ def gw5_add_hclk_bels(dat, dev, device):
portmap = clkdiv2.setdefault('inputs', {})
portmap['RESETN'] = f'B{i + 2}' # GW5A-25A 0-B2, 1-B3, 2-B4, 3-B5
portmap['HCLKIN'] = f'CLKDIV2_HCLKIN{hclk_idx}{i}'
src = f'HCLK_BUF_BO{hclk_idx}{i}'
dest = portmap['HCLKIN']
add_node(dev, f'HCLK{hclk_idx}_{src}', "GLOBAL_CLK", row, col, src)
add_node(dev, f'HCLK{hclk_idx}_{src}', "GLOBAL_CLK", row, col, dest)
if i % 2 == 0:
src = f'HCLK_BUF_BO{hclk_idx}{i}'
dest = portmap['HCLKIN']
add_node(dev, f'HCLK{hclk_idx}_{src}', "GLOBAL_CLK", row, col, src)
add_node(dev, f'HCLK{hclk_idx}_{src}', "GLOBAL_CLK", row, col, dest)
else:
src = f'CLKDIV2_I{hclk_idx}{i}'
dest = portmap['HCLKIN']
make_hclk_pip(dev, hclk_idx, row, col, src, dest)

portmap = clkdiv2.setdefault('outputs', {})
portmap['CLKOUT'] = f'CLKDIV2_O{hclk_idx}{i}'
Expand Down
4 changes: 4 additions & 0 deletions apycula/wirenames.py
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Original file line number Diff line number Diff line change
Expand Up @@ -380,6 +380,10 @@

hclknames_5a25a.update({n: f"HCLK_UNK{n}" for n in range(2, 6 * 187 + 4 * 65)})

# CLKDIV2 inputs
for i in range(2):
hclknames_5a25a[86 + i] = f'CLKDIV2_I{1 + i * 2 }{1 + i}'

# CLKDIV2 outputs
for i in range(4):
hclknames_5a25a[88 + i] = f'CLKDIV2_O0{i}'
Expand Down
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