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aleury
approved these changes
Feb 20, 2026
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This adds a 'signal' mechanism to the core
Machineso that CPUs can support arbitrary signal pins. Also adds simple signal handlers to the 6502 implementation for the NMI, IRQ, and RESET pins that jump to the hard-wired interrupt vectors at $FFFA/FB (NMI), $FFC/FD (RESET), and $FFFE/FF (IRQ/BRK). This implementation does not push PC and SP, or set the B flag on BRK (this is TODO).See https://www.pagetable.com/?p=410 for more details about the real silicon.