Popular repositories Loading

1. portfolio portfolio Public

   HTML

2. cache-simulator cache-simulator Public

   Configurable L1+L2 cache hierarchy simulator with LRU replacement and write-back/write-allocate policy, written in C++

   C++

3. branch-predictor branch-predictor Public

   Dynamic branch predictor simulator supporting Bimodal, GShare, and Hybrid prediction schemes with 2-bit saturating counters, written in C++

   C++

4. dynamic-instruction-scheduler dynamic-instruction-scheduler Public

   Out-of-order processor pipeline simulator with configurable ROB, IQ, and dispatch width

   C++

5. cnn-hardware-accelerator cnn-hardware-accelerator Public

   RTL CNN accelerator in SystemVerilog with 4x4 convolution, leaky ReLU, and 2x2 average pooling for 1024x1024 images

   SystemVerilog