This repository is a curated tutorial package for showing how hardware specifications can be turned into real, tool-verified HLS implementations through a vibe-coding loop:
specification -> prompt -> LLM candidate -> correctness test -> Vitis HLS report -> accept or reject
The package contains two complete demos, retained prompts and LLM responses, candidate source code, Vitis/Vivado reports, and a curated RTL reference for comparison.
| Demo | Goal | Main evidence | Result |
|---|---|---|---|
| Systolic array HLS | Improve throughput for a 16x16 matrix-multiply kernel | Vitis HLS latency, interval, estimated GOPS, resource report | 0.0754 GOPS -> 41.6614 GOPS, 552.7x throughput improvement |
| RISC-V HLS step kernel | Reduce controller resources while preserving correctness | Vitis HLS LUT, FF, latency, interval, C simulation | area score 1035 -> 664, 35.8% reduction |
| DAC2 RTL comparison | Compare conventional RTL handoff against the HLS vibe-coding flow | Vivado OOC reports and curated RTL/docs | Keeps measurement domains explicit and numeric |
The point of the demo is not to trust generated code. The point is to show a disciplined engineering loop where every LLM-generated change is checked by tests and synthesis reports before it is accepted.
-
Follow the live demo runbook:
docs/demo_runbook.md -
Review the numeric comparison:
comparison/DAC2_vs_Vibe_HLS_Numeric_Comparison.md -
Inspect the retained prompt transcripts and measured reports:
demos/systolic-throughput/ demos/riscv-resource/
| Path | Purpose |
|---|---|
docs/ |
Demo runbook, artifact inventory, and upload checklist |
demos/systolic-throughput/ |
Throughput-oriented HLS vibe-coding demo for the systolic array |
demos/riscv-resource/ |
Resource-oriented HLS vibe-coding demo for the RISC-V step kernel |
comparison/ |
DAC2 RTL vs vibe-coding HLS numeric comparison and Vivado reports |
reference-models/ |
Behavioral C reference models, specs, tests, and golden data |
rtl-reference/ |
Curated DAC2 RTL reference, docs, and reports |
scripts/ |
Release-package validation tools |
The fastest replay does not require Vitis or Ollama. It prints the frozen prompt/code/report trajectory from retained artifacts.
cd demos/systolic-throughput
python scripts/vibe_coding_demo.py --compact
python scripts/reproduce_demo.py --mode summarycd demos/riscv-resource
python scripts/reproduce_resource_demo.py --mode summaryFull HLS reproduction requires:
- Python 3
- AMD Vitis HLS 2024.2
- target device
xc7z020-clg400-1 - 10 ns HLS clock constraint
Optional fresh LLM generation requires:
- local Ollama server
- the tested local model was
qwen3-coder:30b
Fresh LLM output is not guaranteed to match the frozen trajectory exactly, even at low temperature, because model/runtime versions can change. The retained prompts, responses, candidate sources, and reports are the audit trail for the demonstrated run.
This is a GitHub review package, not a raw workspace dump. The following are intentionally excluded:
- Vitis/Vivado/OpenLane generated work directories
- presentation files, PPTX files, and speaker notes
.discovery/,.Xil/,.codex/,.agents/, nested.git/- zip archives and old downloaded packages
- OpenLane layout sweep intermediate files from DAC2
- Python
__pycache__/and build executables - internal hardware-spec
.docxfiles unless separately approved
The curated package is small enough for normal GitHub review while preserving the evidence needed to explain and audit the tutorial.
The systolic-array comparison and RISC-V comparison do not claim that every implementation has identical abstraction, interface, and target assumptions.
- DAC2 RTL uses a conventional RTL handoff path and Vivado out-of-context synthesis.
- The vibe-coding demos use Vitis HLS and accept candidates only after correctness and QoR checks.
- DAC2 layout numbers are ASIC/OpenLane context and should not be directly compared to FPGA LUT/FF/DSP numbers.
Use the comparison as a methodology and evidence discussion, not as a simplistic absolute ranking.