Project 02 - Logisim RISC-V CPU

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
code		code
lib		lib
tests		tests
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
alu-harness.circ		alu-harness.circ
alu.circ		alu.circ
check		check
cpu.circ		cpu.circ
logisim.jar		logisim.jar
memory.circ		memory.circ
pc.circ		pc.circ
regfile-harness.circ		regfile-harness.circ
regfile.circ		regfile.circ
riscv.circ		riscv.circ
self check.txt		self check.txt

Provide feedback