Add critical path pass

Cargo.toml

@@ -46,9 +46,9 @@ toml = "0.9.11"
 thiserror = { version = "2.0.16" }
 sv-parser = "0.13.4"
 ctrlc = "3.5.1"
-safety-net = { version = "0.5.5", features = ["graph"] }
+safety-net = { version = "0.6.0", features = ["graph"] }
 good_lp = { version = "1.14.2", optional = true }
-nl-compiler = { version = "0.1.15" }
+nl-compiler = { version = "0.1.16" }
 
 [lints.clippy]
 manual_range_contains = "allow"

src/bin/nl_opt.rs

@@ -4,7 +4,8 @@ use eqmap::pass::{Error, Pass, PrintVerilog};
 use eqmap::register_passes;
 use eqmap::verilog::sv_parse_wrapper;
 use nl_compiler::{from_vast, from_vast_overrides};
-use safety_net::{Identifier, Instantiable, MultiDiGraph, Netlist, SimpleCombDepth, format_id};
+use safety_net::graph::{CombDepthInfo, MultiDiGraph};
+use safety_net::{Identifier, Instantiable, Netlist, format_id};
 use std::io::Read;
 use std::path::PathBuf;
 use std::rc::Rc;
@@ -130,24 +131,71 @@ impl Pass for ReportSccs {
     }
 }
 
-// Report the longest  path in the netlist
-
+/// Report the longest path in the netlist
 pub struct ReportDepth;
 
 impl Pass for ReportDepth {
     type I = PrimitiveCell;
     fn run(&self, netlist: &Rc<Netlist<Self::I>>) -> Result<String, Error> {
-        let analysis = netlist.get_analysis::<SimpleCombDepth<_>>()?;
-        match analysis.get_max_depth() {
-            Some(depth) => Ok(format!("Maximum combinational depth: {depth}")),
-            None => Ok("Maximum combinational depth: undefined".to_string()),
+        let analysis = netlist.get_analysis::<CombDepthInfo<_>>()?;
+
+        if analysis.get_max_depth().is_none() {
+            return Ok("Circuit is ill-formed".to_string());
+        }
+
+        let depth = analysis.get_max_depth().unwrap();
+        let mut res = format!("Maximum combinational depth is {depth}\n");
+
+        for mut p in analysis.get_critical_points().into_iter().cloned() {
+            let mut line = format!("{p}\n");
+            let mut depth = "  ".to_string();
+            while let Some(next) = analysis.get_crit_input(&p) {
+                p = next.get_driver().unwrap().unwrap();
+                line.push_str(&format!("{depth}<- {p}\n"));
+                depth.push_str("  ");
+            }
+            line.push_str(&depth);
+            line.push_str("<- INPUT\n");
+            res.push_str(&line);
+        }
+        Ok(res)
+    }
+}
+
+/// Mark the node names of cells along the critical path
+pub struct MarkCriticalPath;
+
+impl Pass for MarkCriticalPath {
+    type I = PrimitiveCell;
+    fn run(&self, netlist: &Rc<Netlist<Self::I>>) -> Result<String, Error> {
+        let analysis = netlist.get_analysis::<CombDepthInfo<_>>()?;
+
+        if analysis.get_max_depth().is_none() {
+            return Ok("Circuit is ill-formed. No cells marked.".to_string());
+        }
+
+        let p = analysis.build_critical_path();
+
+        if p.is_none() {
+            return Ok("Circuit is ill-formed. No cells marked.".to_string());
         }
+
+        let p = p.unwrap();
+        let l = p.len();
+
+        for c in p {
+            let suffix = c.get_instance_name().unwrap();
+            let prefix: Identifier = "crit_".into();
+            c.set_instance_name(prefix + suffix);
+        }
+
+        Ok(format!("Marked {} cells as critical", l))
     }
 }
 
 register_passes!(PrimitiveCell; PrintVerilog, DotGraph, Clean, DisconnectRegisters,
                                 DisconnectArcSet, MarkArcSet, RenameNets, ReportSccs,
-                                ReportDepth);
+                                ReportDepth, MarkCriticalPath);
 
 /// Netlist optimization debugging tool
 #[derive(Parser, Debug)]
@@ -228,7 +276,9 @@ fn main() -> std::io::Result<()> {
                     if args.verify {
                         f.verify().map_err(std::io::Error::other)?;
                     }
-                    eprintln!("INFO: {pass}: {}", output)
+                    for line in output.lines() {
+                        eprintln!("INFO: {pass}: {}", line)
+                    }
                 }
             }
             Err(Error::IoError(e)) => return Err(e),

src/netlist.rs

@@ -11,7 +11,7 @@ use crate::verilog::PrimitiveType;
 use bitvec::field::BitField;
 use egg::{Id, RecExpr, Symbol};
 use nl_compiler::FromId;
-use safety_net::MultiDiGraph;
+use safety_net::graph::MultiDiGraph;
 use safety_net::{
     Analysis, DrivenNet, Error, Identifier, Instantiable, Logic, Net, Netlist, Parameter,
     format_id, iter::NetDFSIterator,