Logging

Cargo.toml

@@ -49,6 +49,8 @@ ctrlc = "3.5.1"
 safety-net = { version = "0.6.3", features = ["graph"] }
 good_lp = { version = "1.14.2", optional = true }
 nl-compiler = { version = "0.1.18" }
+log = "0.4.29"
+simplelog = "0.12.2"
 
 [lints.clippy]
 manual_range_contains = "allow"

src/bin/eqmap_asic.rs

@@ -3,11 +3,12 @@ use clap::Parser;
 use clap::ValueEnum;
 use eqmap::{
     asic::{CellAnalysis, CellLang, CellRpt, expansion_rewrites, expr_is_mapped},
-    driver::{SynthRequest, process_expression},
+    driver::{SynthRequest, logger_init, process_expression},
     netlist::{LogicMapper, PrimitiveCell},
     rewrite::RewriteManager,
     verilog::sv_parse_wrapper,
 };
+use log::{debug, info, warn};
 use nl_compiler::from_vast;
 use std::{
     io::{Read, Write, stderr, stdin},
@@ -23,7 +24,7 @@ enum Solver {
     Highs,
 }
 
-/// EqMap: ASIC Technology Mapping w/ E-Graphs
+/// ASIC Technology Mapping Optimization with E-Graphs
 #[derive(Parser, Debug)]
 #[command(version, long_about = None)]
 struct Args {
@@ -90,15 +91,17 @@ struct Args {
 
 fn main() -> std::io::Result<()> {
     let args = Args::parse();
+    logger_init(args.verbose);
 
     if cfg!(debug_assertions) {
-        eprintln!("WARNING: Debug assertions are enabled");
+        warn!("Debug assertions are enabled");
     }
 
-    eprintln!("INFO: ASIC Technology Mapping Optimization with E-Graphs");
+    eprintln!("ASIC Technology Mapping Optimization with E-Graphs");
+    info!("ASIC Technology Mapping Optimization with E-Graphs");
 
     let full_command = std::env::args().collect::<Vec<_>>().join(" ");
-    eprintln!("INFO: {}", full_command);
+    info!("{}", full_command);
 
     let mut buf = String::new();
 
@@ -108,7 +111,7 @@ fn main() -> std::io::Result<()> {
             Some(p)
         }
         None => {
-            eprintln!("INFO: Reading from stdin...");
+            info!("Reading from stdin...");
             stdin().read_to_string(&mut buf)?;
             None
         }
@@ -118,8 +121,8 @@ fn main() -> std::io::Result<()> {
 
     let f = from_vast(&ast).map_err(std::io::Error::other)?;
 
-    eprintln!(
-        "INFO: Module {} has {} outputs",
+    info!(
+        "Module {} has {} outputs",
         f.get_name(),
         f.get_output_ports().len()
     );
@@ -141,7 +144,7 @@ fn main() -> std::io::Result<()> {
         root.join("rules/asic.celllang")
     };
 
-    eprintln!("INFO: Loading rewrite rules from {path:?}");
+    info!("Loading rewrite rules from {path:?}");
 
     let mut rules = RewriteManager::<CellLang, CellAnalysis>::new();
     let file = std::fs::File::open(path)?;
@@ -158,13 +161,11 @@ fn main() -> std::io::Result<()> {
         rules.enable_category("expansion_rewrites");
     }
 
-    if args.verbose {
-        eprintln!(
-            "INFO: Running with {} rewrite rules. Hash: {}",
-            rules.num_active(),
-            rules.rules_hash()
-        );
-    }
+    debug!(
+        "Running with {} rewrite rules. Hash: {}",
+        rules.num_active(),
+        rules.rules_hash()
+    );
 
     let rules = rules.active_rules();
 
@@ -231,7 +232,7 @@ fn main() -> std::io::Result<()> {
         ));
     }
 
-    eprintln!("INFO: Compiling Verilog...");
+    info!("Compiling Verilog...");
     let mut mapper = f
         .get_analysis::<LogicMapper<CellLang, PrimitiveCell>>()
         .map_err(std::io::Error::other)?;
@@ -240,8 +241,8 @@ fn main() -> std::io::Result<()> {
     let mapping = mapping.pop().unwrap();
     let expr = mapping.get_expr();
 
-    eprintln!("INFO: Building e-graph...");
-    let result = process_expression::<CellLang, _, CellRpt>(expr, req, true, args.verbose)?
+    info!("Building e-graph...");
+    let result = process_expression::<CellLang, _, CellRpt>(expr, req, true)?
         .with_name(f.get_name().as_str());
 
     if !(args.no_assert || expr_is_mapped(result.get_expr())) {
@@ -256,7 +257,7 @@ fn main() -> std::io::Result<()> {
         result.print_report(&mut stderr().lock())?;
     }
 
-    eprintln!("INFO: Writing output to Verilog...");
+    info!("Writing output to Verilog...");
     let mapping = mapping.with_expr(result.get_expr().to_owned());
     mapping.rewrite(&f).map_err(std::io::Error::other)?;
 
@@ -269,7 +270,7 @@ fn main() -> std::io::Result<()> {
             env!("CARGO_PKG_VERSION"),
             f
         )?;
-        eprintln!("INFO: Goodbye");
+        info!("Goodbye");
     } else {
         print!("{f}");
     }

src/bin/eqmap_fpga.rs

@@ -4,12 +4,13 @@ use clap::ValueEnum;
 #[cfg(feature = "dyn_decomp")]
 use eqmap::rewrite::dyn_decompositions;
 use eqmap::{
-    driver::{SynthReport, SynthRequest, process_expression},
+    driver::{SynthReport, SynthRequest, logger_init, process_expression},
     lut::LutLang,
     netlist::{LogicMapper, PrimitiveCell},
     rewrite::{all_static_rules, register_retiming},
     verilog::sv_parse_wrapper,
 };
+use log::{debug, info, warn};
 use nl_compiler::from_vast_overrides;
 use safety_net::Identifier;
 use std::{
@@ -119,15 +120,17 @@ fn xilinx_overrides(id: &Identifier, cell: &PrimitiveCell) -> Option<PrimitiveCe
 
 fn main() -> std::io::Result<()> {
     let args = Args::parse();
+    logger_init(args.verbose);
 
     if cfg!(debug_assertions) {
-        eprintln!("WARNING: Debug assertions are enabled");
+        warn!("Debug assertions are enabled");
     }
 
-    eprintln!("INFO: EqMap (FPGA Technology Mapping w/ E-Graphs)");
+    eprintln!("EqMap: FPGA Technology Mapping w/ E-Graphs");
+    info!("EqMap: FPGA Technology Mapping w/ E-Graphs");
 
     let full_command = std::env::args().collect::<Vec<_>>().join(" ");
-    eprintln!("INFO: {}", full_command);
+    info!("{}", full_command);
 
     let mut buf = String::new();
 
@@ -137,20 +140,20 @@ fn main() -> std::io::Result<()> {
             Some(p)
         }
         None => {
-            eprintln!("INFO: Reading from stdin...");
+            info!("Reading from stdin...");
             stdin().read_to_string(&mut buf)?;
             None
         }
     };
 
-    eprintln!("INFO: Parsing Verilog...");
+    info!("Parsing Verilog...");
     let ast = sv_parse_wrapper(&buf, path).map_err(std::io::Error::other)?;
 
-    eprintln!("INFO: Compiling Verilog...");
+    info!("Compiling Verilog...");
     let f = from_vast_overrides(&ast, xilinx_overrides).map_err(std::io::Error::other)?;
 
-    eprintln!(
-        "INFO: Module {} has {} outputs",
+    info!(
+        "Module {} has {} outputs",
         f.get_name(),
         f.get_output_ports().len()
     );
@@ -171,18 +174,16 @@ fn main() -> std::io::Result<()> {
         rules.append(&mut register_retiming());
     }
 
-    if args.verbose {
-        eprintln!("INFO: Running with {} rewrite rules", rules.len());
-        #[cfg(feature = "dyn_decomp")]
-        eprintln!(
-            "INFO: Dynamic Decomposition {}",
-            if args.decomp { "ON" } else { "OFF" }
-        );
-        eprintln!(
-            "INFO: Retiming rewrites {}",
-            if args.no_retime { "OFF" } else { "ON" }
-        );
-    }
+    debug!("Running with {} rewrite rules", rules.len());
+    #[cfg(feature = "dyn_decomp")]
+    debug!(
+        "Dynamic Decomposition {}",
+        if args.decomp { "ON" } else { "OFF" }
+    );
+    debug!(
+        "Retiming rewrites {}",
+        if args.no_retime { "OFF" } else { "ON" }
+    );
 
     let req = SynthRequest::default().with_rules(rules);
 
@@ -260,7 +261,7 @@ fn main() -> std::io::Result<()> {
         ));
     }
 
-    eprintln!("INFO: Extracting logic...");
+    info!("Extracting logic...");
     let mut mapper = f
         .get_analysis::<LogicMapper<LutLang, PrimitiveCell>>()
         .map_err(std::io::Error::other)?;
@@ -273,8 +274,8 @@ fn main() -> std::io::Result<()> {
     let mapping = mapping.pop().unwrap();
     let expr = mapping.get_expr();
 
-    eprintln!("INFO: Building e-graph...");
-    let result = process_expression::<_, _, SynthReport>(expr, req, args.no_verify, args.verbose)?
+    info!("Building e-graph...");
+    let result = process_expression::<_, _, SynthReport>(expr, req, args.no_verify)?
         .with_name(f.get_name().as_str());
 
     if let Some(p) = args.report {
@@ -283,7 +284,7 @@ fn main() -> std::io::Result<()> {
         result.print_report(&mut stderr().lock())?;
     }
 
-    eprintln!("INFO: Writing output to Verilog...");
+    info!("Writing output to Verilog...");
     let mapping = mapping.with_expr(result.get_expr().to_owned());
     mapping.rewrite(&f).map_err(std::io::Error::other)?;
 
@@ -296,7 +297,7 @@ fn main() -> std::io::Result<()> {
             env!("CARGO_PKG_VERSION"),
             f
         )?;
-        eprintln!("INFO: Goodbye");
+        info!("Goodbye");
     } else {
         print!("{f}");
     }

src/bin/nl_opt.rs

@@ -1,8 +1,10 @@
 use clap::Parser;
+use eqmap::driver::logger_init;
 use eqmap::netlist::PrimitiveCell;
 use eqmap::pass::{Error, Pass, PrintVerilog};
 use eqmap::register_passes;
 use eqmap::verilog::sv_parse_wrapper;
+use log::{info, warn};
 use nl_compiler::{from_vast, from_vast_overrides};
 use safety_net::graph::{CombDepthInfo, MultiDiGraph};
 use safety_net::{Identifier, Instantiable, Netlist, format_id};
@@ -231,12 +233,13 @@ fn xilinx_overrides(id: &Identifier, cell: &PrimitiveCell) -> Option<PrimitiveCe
 
 fn main() -> std::io::Result<()> {
     let args = Args::parse();
+    logger_init(false);
 
     if cfg!(debug_assertions) {
-        eprintln!("WARNING: Debug assertions are enabled");
+        warn!("Debug assertions are enabled");
     }
 
-    eprintln!("INFO: Netlist optimization debugging tool");
+    info!("Netlist optimization debugging tool");
 
     let mut buf = String::new();
 
@@ -246,16 +249,16 @@ fn main() -> std::io::Result<()> {
             Some(p)
         }
         None => {
-            eprintln!("INFO: Reading from stdin...");
+            info!("Reading from stdin...");
             std::io::stdin().read_to_string(&mut buf)?;
             None
         }
     };
 
-    eprintln!("INFO: Parsing Verilog...");
+    info!("Parsing Verilog...");
     let ast = sv_parse_wrapper(&buf, path).map_err(std::io::Error::other)?;
 
-    eprintln!("INFO: Compiling Verilog...");
+    info!("Compiling Verilog...");
     let f = if !args.no_xilinx {
         from_vast_overrides(&ast, xilinx_overrides).map_err(std::io::Error::other)?
     } else {
@@ -265,7 +268,7 @@ fn main() -> std::io::Result<()> {
     let n = args.passes.len();
 
     for (i, pass) in args.passes.into_iter().enumerate() {
-        eprintln!("INFO: Running pass {i} ({pass})...");
+        info!("Running pass {i} ({pass})...");
         let pass_instance = pass.get_pass();
         match pass_instance.run(&f) {
             Ok(output) => {
@@ -277,7 +280,7 @@ fn main() -> std::io::Result<()> {
                         f.verify().map_err(std::io::Error::other)?;
                     }
                     for line in output.lines() {
-                        eprintln!("INFO: {pass}: {}", line)
+                        info!("{pass}: {}", line)
                     }
                 }
             }

src/bin/opt.rs

@@ -6,11 +6,11 @@ use egg::*;
 use eqmap::rewrite::dyn_decompositions;
 use eqmap::{
     analysis::LutAnalysis,
-    driver::{SynthReport, SynthRequest, process_string_expression, simple_reader},
-    lut,
-    lut::LutLang,
+    driver::{SynthReport, SynthRequest, logger_init, process_string_expression, simple_reader},
+    lut::{self, LutLang},
     rewrite::{all_static_rules, register_retiming},
 };
+use log::{debug, warn};
 use std::path::PathBuf;
 
 fn get_main_runner(
@@ -130,9 +130,10 @@ struct Args {
 
 fn main() -> std::io::Result<()> {
     let args = Args::parse();
+    logger_init(args.verbose);
 
     if cfg!(debug_assertions) {
-        eprintln!("WARNING: Debug assertions are enabled");
+        warn!("Debug assertions are enabled");
     }
 
     let buf = simple_reader(args.command, args.input)?;
@@ -153,14 +154,12 @@ fn main() -> std::io::Result<()> {
         rules.append(&mut register_retiming());
     }
 
-    if args.verbose {
-        eprintln!("INFO: Running with {} rewrite rules", rules.len());
-        #[cfg(feature = "dyn_decomp")]
-        eprintln!(
-            "INFO: Dynamic Decomposition {}",
-            if args.decomp { "ON" } else { "OFF" }
-        );
-    }
+    debug!("Running with {} rewrite rules", rules.len());
+    #[cfg(feature = "dyn_decomp")]
+    debug!(
+        "Dynamic Decomposition {}",
+        if args.decomp { "ON" } else { "OFF" }
+    );
 
     let req = SynthRequest::default().with_rules(rules).with_k(args.k);
 
@@ -226,12 +225,8 @@ fn main() -> std::io::Result<()> {
     };
 
     for line in buf.lines() {
-        let result = process_string_expression::<_, _, SynthReport>(
-            line,
-            req.clone(),
-            args.no_verify,
-            args.verbose,
-        )?;
+        let result =
+            process_string_expression::<_, _, SynthReport>(line, req.clone(), args.no_verify)?;
         if !result.is_empty() {
             println!("{result}");
         }