Currently it's the default to create a stitched IP so that in the VitisBuild step, you usually have three kernels: IDMA, StreamingDataflowPartition_0 and ODMA. This however prevents effective debugging in hardware, atleast when using the v++ provided --debug option, with which you can automatically insert a Logic Analyzer to watch the ports of the instantiated CUs. But since the current flow only creates a single SDP, monitoring and debugging of the different stages of the dataflow pipeline is not possible.
I'd propose to add an option to either pack the whole pipeline into one SDP (current default), or to pack every node into it's own SDP and let the linker config take care of connecting the kernel instead of SDP internal AXI streams. This would enable a much more fine granular insertion of ILAs. This could probably be done as part of #27.
Currently it's the default to create a stitched IP so that in the VitisBuild step, you usually have three kernels:
IDMA,StreamingDataflowPartition_0andODMA. This however prevents effective debugging in hardware, atleast when using thev++provided--debugoption, with which you can automatically insert a Logic Analyzer to watch the ports of the instantiated CUs. But since the current flow only creates a single SDP, monitoring and debugging of the different stages of the dataflow pipeline is not possible.I'd propose to add an option to either pack the whole pipeline into one SDP (current default), or to pack every node into it's own SDP and let the linker config take care of connecting the kernel instead of SDP internal AXI streams. This would enable a much more fine granular insertion of ILAs. This could probably be done as part of #27.