DLX CPU

Simple educational MIPS-like (RISC), in-order, pipelined CPU developed during the Microelectronic Systems course at Politecnico di Torino.

DLX Architecture

The CPU is organized in a 5-stage MIPS-like Datapath, plus a Hardwired Control Unit. Instruction and Data memories are also included for storing a program and storing results, respectively.

Following are diagrams depicting every portion of the CPU in detail. Each name matches exactly the one used inside VHDL source files.

Top-view:

Datapath:

Control Unit:

Testbench:

Project Structure

The project is organized as follows:

• assembler.bin/: Pre-built basic assembler:

  • dlxasm.pl: Assembler to convert written programs into binary code.
  • conv2memory: Script to convert the generated executable program into .mem format.

• img/: Contains README diagrams.

• programs/: Test programs to check every CPU functionality works correctly.

• run/: Directory containing the main run script and various utility scripts:

  • colors.sh: Colored terminal print utilities.
  • vhdl_utils.sh: Bash utility functions to get the Testbench's top entity name and architecture name. Allows the run script not to use hardcoded strings.
  • vsim_run_sim.do: TCL script to add visual dividers and signals into QuestaSim's Signals pane for a more organized signals visualization.
  • run.sh: Main run script, compiles all VHDL source files and then starts a QuestaSim simulation.

• src/: Directory containing the following source VHDL files:

  • Packages:
    • 000-pkg-globals.vhd: Package for enumerating all ALU operation OPCODEs.
    • 001-pkg-registerfile.vhd: Package containing a log2 function used for Register File.
  • Datapath:
    • ALU:
      • a.b.a-ALU.vhd: ALU capable of performing ADDition, SUBtraction, logical operations (AND, OR, XOR), "SET IF" operations, Shift operations, and Rotate operations.
      • a.b.a.a-generic_shifter.vhd: Shift/Rotate component used by ALU.
    • a.b.b-DRAM.vhd: Combinational Data Memory for storing operations results.
    • a.b.c-SignExtender26-32.vhd: Sign extender (26 to 32 bits) for extending "jump-type" immediates on 26 bits as signed.
    • a.b.c-UnsignExtender26-32.vhd: Sign extender (26 to 32 bits) for extending "jump-type" immediates on 26 bits as unsigned.
    • a.b.d-MUX.vhd: Basic N-bit multiplexer.
    • a.b.e-PC_Add.vhd: Custom adder, specifically sized and operated to only increment the content of the Program Counter register to address the next instruction in (Instruction) Memory.
    • a.b.f-RegisterFile.vhd: Dual-port basic Register File.
    • a.b.g-FlipFlop.vhd: Basic N-bit flip flop/register.
    • a.b.h-SignExtender16-32.vhd: Sign extender (16 to 32 bits) for extending "immediate-type" immediates on 16 bits for both signed and unsigned operands.
    • a.b.i-ZeroComparator.vhd: Component used to check whether the operand is zero or not, depending on the branch flags passed as inputs.
    • a.c-IRAM.vhd: Instruction Memory used to store the program which will be executed by the CPU.

• test_bench/: Contains various testbenches for the most important components of the CPU, for testing each one individually, aside from the testbench to use (TB_DLX.vhd) for running a program on the DLX via simulation.

License

This project is licensed under the MIT License - see the LICENSE file for details.