Optimize SiLU for Ascend and MetaX

[YUANXIGUREN]

PR Category

Operator, OP Test, Benchmark

Type of Change

Bug Fix, Performance Optimization

Description

Optimize SiLU for Ascend 910C and MetaX C550.

The Ascend implementation uses a vendor pointwise configuration with a tile
size of 4096 and fixes output-layout behavior for non-contiguous inputs.

The MetaX implementation uses one unified tile-2048 route with balanced-grid
partitioning. Unsupported dtypes and non-contiguous inputs continue through
the common implementation. No dtype- or size-based tier is used.

Six general large shapes are added to the public benchmark and correctness
coverage.

Issue

N/A

Progress

• Change is properly reviewed.
• Change is responded to an issue.
• Change is fully covered by UT.

Correctness

Platform	Result
Ascend 910C	Candidate: 84 passed; Official: 81 passed, 3 non-contiguous-layout failures
MetaX C550	Candidate tests/test_silu.py: 100 passed
Added public cases	Six shapes across FP32, FP16 and BF16

Environment

Platform	Python	Torch stack	Runtime
Ascend 910C	3.11.14	torch 2.8.0+cpu, torch_npu 2.8.0.post2, Triton 3.2.0	CANN 8.5
MetaX C550	Python 3	torch 2.8.0+metax3.3.0.2, Triton 3.1.0	MetaX C550

Performance

Speedup is Official FlagGems latency divided by this PR latency.

Platform	Scope	FP32	FP16	BF16
Ascend 910C	Public 20-shape SiLU	1.351x	1.359x	1.341x
MetaX C550	Public 20-shape SiLU	1.036x	1.106x	1.108x

The GraphCast results are operator-level weighted microbenchmarks over seven
real shapes, not complete model end-to-end measurements.

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