[XPU] Sync internal 5a664566 cluster + SDNN v0.3.6.7.0 and conceal IR - #992
Open
dongjibin1996 wants to merge 13 commits into
Open
[XPU] Sync internal 5a664566 cluster + SDNN v0.3.6.7.0 and conceal IR#992dongjibin1996 wants to merge 13 commits into
dongjibin1996 wants to merge 13 commits into
Conversation
dongjibin1996
requested review from
Galaxy1458,
menchunlei,
sunnycase and
zhzhcookie
as code owners
August 14, 2026 09:05
github-actions
Bot
added
DOC
dongjibin1996
force-pushed
the
xpu-sync-internal-5a664566
branch
2 times, most recently
from
August 14, 2026 10:32
3fd166e to
8b7db98
Compare
Import Scalar/Tile/Vectorizability analysis and the new XPU-only passes (Normalize, AsyncLoadSchedule, TLELegalize, LoopInvariantStaging, LegalizeExternEW). Add stage_sm / load_scalar_indexed ops plus GM2SM lowering. Preserve handwritten OffsetAnalysis attrs and keep budget-tiling / loop-invariant-staging off by default. Source: baidu/xpu/triton 6848085b..5a664566. SDNN/.a artifacts are not included.
The C++ binding now requires vrf_budget/budget_tiling/pin_unroll_num. Keep budget tiling off and pin_unroll_num=-1 so vector-add stays on the legacy unroll path.
Merge OffsetAnalysis GetNumPrograms/remsi/handwritten recovery, Scan loop-carry lowering, CoreTiling TypeSwitch getChain, UnrollControl budget model, and LM-only DMA mfence. Drop Pack/Unpack and GetEnv whitelist usage so FlagTree still compiles. P800 vector-add stays max_abs_err=0.0. SDNN artifacts are harvested but not installed.
Extend add_xpu_sdnn_object(TritonSDNNTransforms) to the full internal source list (34 objects). Prebuilt .o files stay gitignored and are installed from the rebuilt artifact dir.
5a664566 TritonSDNNToLLVM.cpp.o needs translateLLVMIRToModule. Keep the dependency on the XPU SDNN target, not the main tree.
Pass load_tile_size into convert-triton-to-tritonsdnn and wire the new SDNN transform passes so mm kernels can compile against the rebuilt objects.
Point xpu.py at the 5a664566 SDNN package. The tarball includes the CombineBefore getenv fix, the v0.3.6.6.0 translation ABI object, and the 28-member libTritonSharedForXPU.a.
Guard XPU ir.cc printers and enable_debug with TRITON_CONCEAL_IR so MLIR_ENABLE_DUMP emits no per-pass IR. Define the macro from third_party/xpu/CMakeLists.txt for XPU Release builds only.
FlagTree default build type is TritonRelBuildWithAsserts, which does not inherit CMAKE_CXX_FLAGS_RELEASE. Define the macro for that config and all non-Debug XPU builds so MLIR_ENABLE_DUMP stays off.
ir.cc is compiled by the top-level triton target, so directory flags in third_party/xpu never reached it. Defer target_compile_definitions onto triton after it is created.
Rebuild XPUToIRTranslationForSDNN.o against llvm_trust from internal 5a664566, and refresh libdevice-xpu3s.bc / liblaunch.a from the same tip. P800 vector-add and fp16 mm stay max_abs_err=0.0.
dongjibin1996
force-pushed
the
xpu-sync-internal-5a664566
branch
from
August 14, 2026 10:44
8b7db98 to
d1fe1a9
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Sync FlagTree XPU from internal Triton
triton_3.6tip5a664566, rebased ontoxpu/triton-3.6-migration(100abf4).MLIR_ENABLE_DUMPin non-Debug XPU builds (TRITON_CONCEAL_IR)v0.3.6.7.1:XPUToIRTranslationForSDNN.orebuilt from5a664566againstllvm_trustlibdevice-xpu3s.bcrebuilt from5a664566with llvm_trust clangliblaunch.afrom internal5a664566backend outputIntentionally not included
isTLEand TLE/Pack/Unpack loweringValidation
max_abs_err=0.0fp16_mm[32,32,32]:max_abs_err=0.0str(module)=0,enable_debug()=FalseunderMLIR_ENABLE_DUMP=1SHA256
50dbd893b50123e4f5331b3d4c99f71e2e346e8a3a1a9a4341b82bac138b310c