fpga-open-speech-tools · tvannoy · Apr 20, 2020
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System.qpf b/AudioMini_AD4020 Demo/DE10Nano_System.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 13:20:18  August 03, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.0"
+DATE = "13:20:18  August 03, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "DE10Nano_System"
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System.qsf b/AudioMini_AD4020 Demo/DE10Nano_System.qsf
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System.sdc b/AudioMini_AD4020 Demo/DE10Nano_System.sdc
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System.vhd b/AudioMini_AD4020 Demo/DE10Nano_System.vhd
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System.vhd.bak b/AudioMini_AD4020 Demo/DE10Nano_System.vhd.bak
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System_assignment_defaults.qdf b/AudioMini_AD4020 Demo/DE10Nano_System_assignment_defaults.qdf
diff --git a/AudioMini_AD4020 Demo/DE10Nano_System_tmp_archive.qarlog b/AudioMini_AD4020 Demo/DE10Nano_System_tmp_archive.qarlog
diff --git a/AudioMini_AD4020 Demo/FE_AD4020_hw.tcl b/AudioMini_AD4020 Demo/FE_AD4020_hw.tcl
@@ -0,0 +1,148 @@
+# TCL File Generated by Component Editor 18.0
+# Thu Apr 09 12:50:50 MDT 2020
+# DO NOT MODIFY
+
+
+# 
+# FE_AD4020 "FE_AD4020" v1.0
+#  2020.04.09.12:50:50
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module FE_AD4020
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME FE_AD4020
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME FE_AD4020
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL FE_AD4020_v1
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file FE_AD4020_v1.vhd VHDL PATH ../../component_library/AD4020/Source_Files/FE_AD4020_v1.vhd TOP_LEVEL_FILE
+add_fileset_file spi_abstract.vhd VHDL PATH ../../component_library/SPI/Source_Files/spi_abstract.vhd
+add_fileset_file spi_commands.vhd VHDL PATH ../../component_library/SPI/Source_Files/spi_commands.vhd
+add_fileset_file spi_clk_delay.vhd VHDL PATH ../../component_library/SPI/Source_Files/spi_clk_delay.vhd
+
+
+# 
+# parameters
+# 
+add_parameter input_clk_freq INTEGER 71000000
+set_parameter_property input_clk_freq DEFAULT_VALUE 71000000
+set_parameter_property input_clk_freq DISPLAY_NAME input_clk_freq
+set_parameter_property input_clk_freq TYPE INTEGER
+set_parameter_property input_clk_freq UNITS None
+set_parameter_property input_clk_freq ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property input_clk_freq HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point Line_In
+# 
+add_interface Line_In avalon_streaming start
+set_interface_property Line_In associatedClock sys_clock
+set_interface_property Line_In associatedReset sys_reset
+set_interface_property Line_In dataBitsPerSymbol 32
+set_interface_property Line_In errorDescriptor ""
+set_interface_property Line_In firstSymbolInHighOrderBits true
+set_interface_property Line_In maxChannel 0
+set_interface_property Line_In readyLatency 0
+set_interface_property Line_In ENABLED true
+set_interface_property Line_In EXPORT_OF ""
+set_interface_property Line_In PORT_NAME_MAP ""
+set_interface_property Line_In CMSIS_SVD_VARIABLES ""
+set_interface_property Line_In SVD_ADDRESS_GROUP ""
+
+add_interface_port Line_In AD4020_data_out data Output 32
+add_interface_port Line_In AD4020_error_out error Output 2
+add_interface_port Line_In AD4020_valid_out valid Output 1
+add_interface_port Line_In AD4020_channel_out channel Output 2
+set_interface_assignment Line_In channel 0
+
+
+# 
+# connection point connect_to_ad4020
+# 
+add_interface connect_to_ad4020 conduit end
+set_interface_property connect_to_ad4020 associatedClock spi_clk
+set_interface_property connect_to_ad4020 associatedReset sys_reset
+set_interface_property connect_to_ad4020 ENABLED true
+set_interface_property connect_to_ad4020 EXPORT_OF ""
+set_interface_property connect_to_ad4020 PORT_NAME_MAP ""
+set_interface_property connect_to_ad4020 CMSIS_SVD_VARIABLES ""
+set_interface_property connect_to_ad4020 SVD_ADDRESS_GROUP ""
+
+add_interface_port connect_to_ad4020 AD4020_CONV_out cnv Output 1
+add_interface_port connect_to_ad4020 AD4020_MISO_in miso Input 1
+add_interface_port connect_to_ad4020 AD4020_MOSI_out mosi Output 1
+add_interface_port connect_to_ad4020 AD4020_SCLK_out sclk Output 1
+
+
+# 
+# connection point sys_reset
+# 
+add_interface sys_reset reset end
+set_interface_property sys_reset associatedClock sys_clock
+set_interface_property sys_reset synchronousEdges DEASSERT
+set_interface_property sys_reset ENABLED true
+set_interface_property sys_reset EXPORT_OF ""
+set_interface_property sys_reset PORT_NAME_MAP ""
+set_interface_property sys_reset CMSIS_SVD_VARIABLES ""
+set_interface_property sys_reset SVD_ADDRESS_GROUP ""
+
+add_interface_port sys_reset sys_reset_n reset_n Input 1
+
+
+# 
+# connection point sys_clock
+# 
+add_interface sys_clock clock end
+set_interface_property sys_clock clockRate 0
+set_interface_property sys_clock ENABLED true
+set_interface_property sys_clock EXPORT_OF ""
+set_interface_property sys_clock PORT_NAME_MAP ""
+set_interface_property sys_clock CMSIS_SVD_VARIABLES ""
+set_interface_property sys_clock SVD_ADDRESS_GROUP ""
+
+add_interface_port sys_clock sys_clk clk Input 1
+
+
+# 
+# connection point spi_clk
+# 
+add_interface spi_clk clock end
+set_interface_property spi_clk clockRate 0
+set_interface_property spi_clk ENABLED true
+set_interface_property spi_clk EXPORT_OF ""
+set_interface_property spi_clk PORT_NAME_MAP ""
+set_interface_property spi_clk CMSIS_SVD_VARIABLES ""
+set_interface_property spi_clk SVD_ADDRESS_GROUP ""
+
+add_interface_port spi_clk spi_clk clk Input 1
+
diff --git a/AudioMini_AD4020 Demo/FE_AD4020_hw.tcl~ b/AudioMini_AD4020 Demo/FE_AD4020_hw.tcl~
@@ -0,0 +1,162 @@
+# TCL File Generated by Component Editor 18.0
+# Thu Apr 09 11:22:59 MDT 2020
+# DO NOT MODIFY
+
+
+# 
+# FE_AD4020 "FE_AD4020" v1.0
+#  2020.04.09.11:22:59
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module FE_AD4020
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME FE_AD4020
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME FE_AD4020
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL FE_AD4020_v1
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file FE_AD4020_v1.vhd VHDL PATH ../../component_library/AD4020/Source_Files/FE_AD4020_v1.vhd TOP_LEVEL_FILE
+add_fileset_file spi_abstract.vhd VHDL PATH ../../component_library/SPI/Source_Files/spi_abstract.vhd
+add_fileset_file spi_commands.vhd VHDL PATH ../../component_library/SPI/Source_Files/spi_commands.vhd
+add_fileset_file spi_clk_delay.vhd VHDL PATH ../../component_library/SPI/Source_Files/spi_clk_delay.vhd
+
+
+# 
+# parameters
+# 
+add_parameter input_clk_freq INTEGER 71000000
+set_parameter_property input_clk_freq DEFAULT_VALUE 71000000
+set_parameter_property input_clk_freq DISPLAY_NAME input_clk_freq
+set_parameter_property input_clk_freq TYPE INTEGER
+set_parameter_property input_clk_freq UNITS None
+set_parameter_property input_clk_freq ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property input_clk_freq HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point Line_In
+# 
+add_interface Line_In avalon_streaming start
+set_interface_property Line_In associatedClock sys_clock
+set_interface_property Line_In associatedReset sys_reset
+set_interface_property Line_In dataBitsPerSymbol 32
+set_interface_property Line_In errorDescriptor ""
+set_interface_property Line_In firstSymbolInHighOrderBits true
+set_interface_property Line_In maxChannel 0
+set_interface_property Line_In readyLatency 0
+set_interface_property Line_In ENABLED true
+set_interface_property Line_In EXPORT_OF ""
+set_interface_property Line_In PORT_NAME_MAP ""
+set_interface_property Line_In CMSIS_SVD_VARIABLES ""
+set_interface_property Line_In SVD_ADDRESS_GROUP ""
+
+add_interface_port Line_In AD4020_data_out data Output 32
+add_interface_port Line_In AD4020_error_out error Output 2
+add_interface_port Line_In AD4020_valid_out valid Output 1
+add_interface_port Line_In AD4020_channel_out channel Output 2
+set_interface_assignment Line_In channel 0
+
+
+# 
+# connection point connect_to_ad4020
+# 
+add_interface connect_to_ad4020 conduit end
+set_interface_property connect_to_ad4020 associatedClock spi_clk
+set_interface_property connect_to_ad4020 associatedReset sys_reset
+set_interface_property connect_to_ad4020 ENABLED true
+set_interface_property connect_to_ad4020 EXPORT_OF ""
+set_interface_property connect_to_ad4020 PORT_NAME_MAP ""
+set_interface_property connect_to_ad4020 CMSIS_SVD_VARIABLES ""
+set_interface_property connect_to_ad4020 SVD_ADDRESS_GROUP ""
+
+add_interface_port connect_to_ad4020 AD4020_CONV_out cnv Output 1
+add_interface_port connect_to_ad4020 AD4020_MISO_in miso Input 1
+add_interface_port connect_to_ad4020 AD4020_MOSI_out mosi Output 1
+add_interface_port connect_to_ad4020 AD4020_SCLK_out sclk Output 1
+
+
+# 
+# connection point sys_reset
+# 
+add_interface sys_reset reset end
+set_interface_property sys_reset associatedClock sys_clock
+set_interface_property sys_reset synchronousEdges DEASSERT
+set_interface_property sys_reset ENABLED true
+set_interface_property sys_reset EXPORT_OF ""
+set_interface_property sys_reset PORT_NAME_MAP ""
+set_interface_property sys_reset CMSIS_SVD_VARIABLES ""
+set_interface_property sys_reset SVD_ADDRESS_GROUP ""
+
+add_interface_port sys_reset sys_reset_n reset_n Input 1
+
+
+# 
+# connection point sys_clock
+# 
+add_interface sys_clock clock end
+set_interface_property sys_clock clockRate 0
+set_interface_property sys_clock ENABLED true
+set_interface_property sys_clock EXPORT_OF ""
+set_interface_property sys_clock PORT_NAME_MAP ""
+set_interface_property sys_clock CMSIS_SVD_VARIABLES ""
+set_interface_property sys_clock SVD_ADDRESS_GROUP ""
+
+add_interface_port sys_clock sys_clk clk Input 1
+
+
+# 
+# connection point spi_clk
+# 
+add_interface spi_clk clock end
+set_interface_property spi_clk clockRate 0
+set_interface_property spi_clk ENABLED true
+set_interface_property spi_clk EXPORT_OF ""
+set_interface_property spi_clk PORT_NAME_MAP ""
+set_interface_property spi_clk CMSIS_SVD_VARIABLES ""
+set_interface_property spi_clk SVD_ADDRESS_GROUP ""
+
+add_interface_port spi_clk spi_clk clk Input 1
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink double_spi_clk_in clk Input 1
+
diff --git a/AudioMini_AD4020 Demo/__DE10Nano_System.auto.qarlog b/AudioMini_AD4020 Demo/__DE10Nano_System.auto.qarlog
@@ -0,0 +1,25 @@
+Quartus Prime Archive log --	C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/__DE10Nano_System.auto.qarlog
+
+Archive:	C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/__DE10Nano_System.auto.qar
+Date:		Thu Nov 21 12:11:21 2019
+Quartus Prime		18.1.0 Build 625 09/12/2018 SJ Lite Edition
+
+	=========== Files Selected: ===========
+C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/db/DE10Nano_System.cbx.xml
+C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/db/DE10Nano_System.qpf
+C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/output_files/DE10Nano_System.flow.rpt
+C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/output_files/DE10Nano_System.map.rpt
+C:/Users/mc_gr/Desktop/FPGA Open Speech Tools/de10nano_projects/AudioMini_Passthrough/output_files/DE10Nano_System.map.summary
+DE10Nano_System.qsf
+DE10Nano_System.sdc
+DE10Nano_System.vhd
+DE10Nano_System_assignment_defaults.qdf
+DE10Nano_System_tmp_archive.qarlog
+__DE10Nano_System.auto.qarlog
+c:/intelfpga_lite/18.1/quartus/bin64/assignment_defaults.qdf
+soc_system.ipx
+soc_system.qsys
+	======= Total: 14 files to archive =======
+
+	================ Status: ===============
+All files archived successfully.
diff --git a/AudioMini_AD4020 Demo/audio_mini_board_info.xml b/AudioMini_AD4020 Demo/audio_mini_board_info.xml
@@ -0,0 +1,21 @@
+<BoardInfo pov="hps_arm_a9_0">
+<!--
+This file is intended to be used when building device trees
+for the Altera Cyclone5 SOC Development Kits.
+This board info file and hps_clock_info.xml are required input
+to sopc2dts to create a device tree suitable for the 3.9 version
+of the Linux kernel.  One typically executes sopc2dts as follows:
+
+	sopc2dts -i soc_system.sopcinfo -b soc_system_board_info.xml
+		-b hps_clock_info.xml -b hps_common_board_info.xml -o soc_system.dts
+
+-->
+<!-- TPA613A2 headphone amplifier device driver support -->
+<DTAppend name="fe_tpa613a2" type="node" parentlabel="sopc0" newlabel="fe_tpa613a2"/>
+<DTAppend name="compatible" type="string" parentlabel="fe_tpa613a2" val="dev,fe-tpa613a2"/>
+
+<!-- AD1939 codec device driver support -->
+<DTAppend name="fe_ad1939" type="node" parentlabel="sopc0" newlabel="fe_ad1939"/>
+<DTAppend name="compatible" type="string" parentlabel="fe_ad1939" val="dev,fe-ad1939"/>
+
+</BoardInfo>