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Extract all layout related information into a MemoryLayout trait#1409

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jounathaen wants to merge 3 commits into
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mem_layout
Open

Extract all layout related information into a MemoryLayout trait#1409
jounathaen wants to merge 3 commits into
mainfrom
mem_layout

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@jounathaen

@jounathaen jounathaen commented Jul 9, 2026

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The impls. of MemoryLayout (Aarch64MemoryLayout and X86_64MemoryLayout) are basically duplicates, but semantically this makes more sense and also gives us more freedom to modify the layout for architecture-specific features.

Closes #1303

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codecov Bot commented Jul 9, 2026

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Codecov Report

❌ Patch coverage is 92.81437% with 24 lines in your changes missing coverage. Please review.
✅ Project coverage is 79.51%. Comparing base (35a2922) to head (e2bfe20).
⚠️ Report is 6 commits behind head on main.

Files with missing lines Patch % Lines
src/arch/x86_64/mod.rs 88.54% 11 Missing ⚠️
src/mem_layout.rs 96.74% 4 Missing ⚠️
src/arch/x86_64/paging.rs 91.66% 3 Missing ⚠️
src/mem.rs 82.35% 3 Missing ⚠️
src/vm.rs 93.18% 3 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##             main    #1409      +/-   ##
==========================================
+ Coverage   79.50%   79.51%   +0.01%     
==========================================
  Files          38       39       +1     
  Lines        5464     5536      +72     
==========================================
+ Hits         4344     4402      +58     
- Misses       1120     1134      +14     

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@jounathaen
jounathaen force-pushed the mem_layout branch 3 times, most recently from cabfc28 to 33c6e4d Compare July 9, 2026 21:12
@jounathaen jounathaen changed the title refactor: Extract all layout related information into a MemoryLayout … Extract all layout related information into a MemoryLayout trait Jul 9, 2026
@jounathaen
jounathaen force-pushed the mem_layout branch 9 times, most recently from 354b962 to 71859c1 Compare July 14, 2026 08:18

@fogti fogti left a comment

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I'm a bit confused about where guest_address additions were removed and where they weren't, particularly in page table initialization code...

Comment thread src/arch/aarch64/mod.rs
Comment on lines +184 to +185
let pt_size = 512 * size_of::<u64>();
assert!(mem.guest_addr() + mem.size() >= layout.pgt_address() + pt_size);

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Suggested change
let pt_size = 512 * size_of::<u64>();
assert!(mem.guest_addr() + mem.size() >= layout.pgt_address() + pt_size);
const PT_SIZE: usize = 512 * size_of::<u64>();
assert!(mem.guest_addr() + mem.size() >= layout.pgt_address() + PT_SIZE);

Comment thread src/mem_layout.rs
self.addr
}
// "no code using it on aarch64 (yet)"
pub fn end(&self) -> GuestPhysAddr {

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This looks wrong for any underlying T with core::mem::size_of::<T>() != 1.

To ensure correct usage, Section should be tagged with the underlying slice type T using PhantomData, and use self.addr + self.length * core::mem::size_of::<T>() below.

Comment thread src/mem_layout.rs

fn boot_info(&self) -> BootInfoSection;

/// The Starting position of the allocatable pagetables area. This doesn't need to include all pagetables.

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What's the meaning of the length of the returned section? Otherwise, just return an address...

Comment thread src/vm.rs
});

let legacy_mapping = if let Some(version) = hermit_version {
// actually, all versions that have the tag in the elf are valid, but an explicit check doesn't hurt

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What does "valid" mean in his context?

Comment thread src/vm.rs
};
trace!("Initialize guest memory");
VirtBackend::init_guest_mem(
&mut mem, // slice only lives during this fn call

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That's not a slice anymore?

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remove consts.rs

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