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warmup: add batch=3 to MTP uniform decode kernel warmup#23

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warmup: add batch=3 to MTP uniform decode kernel warmup#23
lennytinkeredapps wants to merge 12 commits into
jasl:codex/ds4-sm120-min-enablefrom
lennytinkeredapps:feat/warmup-3-batch-decode-kernels

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Problem

When concurrency climbs to 3+ requests, 10 Triton JIT kernels in the sparse-MLA decode attention path compile mid-inference, causing ~20s latency spikes:

Attention/decode — 3+ batch:

  • _build_combined_decode_valid_mask_kernel
  • _finish_materialized_scores_with_sink_candidate_block_kernel
  • _indexed_d512_split_score_kernel
  • _indexed_d512_split_stats_kernel
  • _indexed_d512_split_value_kernel
  • _accumulate_fp8ds_global_slots_attention_chunk_multihead_kernel
  • _finish_two_attention_states_with_sink_kernel
  • _indexed_d512_chunked_merge_acc_kernel
  • _indexed_d512_chunked_merge_state_kernel
  • _accumulate_indexed_attention_chunk_multihead_kernel

Root Cause

_DEEPSEEK_V4_MTP_UNIFORM_DECODE_WARMUP_REQUESTS = (1, 2, 4, 8, 16, 24, 32) skips batch size 3. The _dummy_run(uniform_decode=True) warmup therefore never exercises the decode attention path at batch=3, so the kernels above are uncompiled until the first 3-concurrent request.

Fix

Add 3 to the warmup tuple: (1, 2, **3**, 4, 8, 16, 24, 32).

This ensures _deepseek_v4_sparse_mla_attention_warmup() calls runner._dummy_run(uniform_decode=True) with num_reqs=3, which triggers the full sparse-MLA decode attention forward path and compiles all listed kernel shapes during startup.

Verification

  • Logic verified: _deepseek_v4_mtp_uniform_decode_warmup_requests() now returns (1, 2, 3, 4, 8, 16, 24, 32, 256) for the c256 case
  • Updated test_deepseek_v4_kernel_warmup.py assertions to expect 3 in all tuples
  • All existing test assertions still pass with updated expected values

Context

Observed on DeepSeek-V4-Flash EP=2 on dual GB10 (SM12x) with 1M context / 32.3GB KV recipe.

Supplements jasl PR vllm-project#41834 — extends warmup coverage to the 3-batch decode shapes.

jasl and others added 12 commits June 20, 2026 22:16
…_STRICT_TOOL_CALLING

Cosmetic reflow churn from 59c7918 on an upstream-owned env; restore
byte-identical to base 0fbf42a. No behavior change.
…eal MiniMax-only gate

The DSv4-out behavior (default FULL_AND_PIECEWISE, 1.5-3.8x faster MTP decode,
measured RTX/SM120 + GB10/SM121) is unchanged. Replaces the dead always-False
_should_auto_enable_deepseek_v4_breakable_cudagraph stub + unused
DEEPSEEK_V4_CUDAGRAPH_ARCHITECTURES frozenset + misleading SM120/SM121 comment
with a single meaningful _should_auto_enable_breakable_cudagraph(model_config)
that returns True only for the MiniMax M3 architectures (upstream's auto-enable
set minus DSv4). Test upgraded from tautological always-False asserts to
observable behavior: DSv4 off, MiniMax on, others off.
Reverts 99a9f10 (whose actual content is solely the gemm-backend env +
_NVFP4_BACKEND_TO_KERNEL force-map, not the modelopt-routing its title names).
The DSv4-Flash shipped path does not use the flashinfer-b12x NVFP4 route; this
env was only a research lever (and the sole working way to reach b12x, since
FlashInferB12xNvFp4LinearKernel is excluded from auto-selection and
--linear-backend flashinfer_b12x is filtered out). Preserved verbatim on
backup/min-enable-88ec-pre-audit-20260620 for future NVFP4-backend experiments;
restore the env+map from that commit to re-enable b12x A/B.
… + tests

Removes the 9-commit very-long-prefill starvation / mixed-decode-prefill chunk
limiting family (a8bdc00, 129e129, a962bf1[sched part], 1059c81,
ad26f8f, db3a71f, 6dac492, 52c549e, 574905a[sched part]) from
scheduler.py: 9 helper methods + 3 call sites; restores the deleted blank line
and the original 'assert num_new_tokens > 0'. Drops the 11 tautological fairness
tests. Ungated generic-vLLM tuning aimed at a cliff re-diagnosed as MoE-GEMM +
NCCL-all-reduce bound (config knobs proven dead on GB10) plus a phantom wedge;
never required for correctness.

Preserved (verified standalone, not fairness-coupled): the write-fence hooks
(20e1472, kept pending the fence-OFF recall gate), max_num_seqs +
DSv4 MLA prefix-retention (fde655c), the a962bf1 adaptive BLOCK_M kernel
tuning in sm12x_mqa.py, and the 574905a record_stats param + its
test_prefix_cache_peek_does_not_record_stats (tests kept kv_cache_manager
stats-suppression behavior). Net: scheduler.py == base except the 3 KEEP hunks;
test_scheduler.py == base except the peek test. Needs RTX long-ctx-concurrency +
GSM8K + toolcall-15 no-regression revalidation.
…ds recall)

GPU-validated 2026-06-21 on the int64-fixed 88ec build: the fence-OFF recall gate
(VLLM_PREFIX_CACHE_WRITE_FENCE=0) holds arthur long-context coherence 8/8 at
conc=8 and 16/16 at conc=16 (MTP2, 0 miss) -- exercising exactly the >=3
concurrent-identical-prefix in-flight hand-off window the fence guarded. So the
write fence is redundant: the int64 block-offset overflow fix (197d21e +
88ec87e) is the real long-context recall fix; the fence was built on the
disproven shared-write/COW theory and its 06-19 commit-message recall claim
(~20%->91%) was masking the then-unfixed int64 bug. Reverts 20e1472
(committed_step/schedule_pass/retired_forward clocks, get_one_block_retired,
the default-on env, and the two scheduler hooks). scheduler.py is now identical
to base except the fde655c max_num_seqs prefix-retention arg.
…83 crash)

PR#41834 user 1zilc crash with VLLM_DEEPSEEK_V4_FLASHINFER_SM120_PREFILL=1:
  tvm.error.InternalError: Check failed: output.size(0) == num_tokens (84 vs 83)
at flashinfer sparse_mla_sm120.cu:183, cascading to a CUDA illegal memory access
that kills EngineCore.

Root cause: the packed _forward_prefill Bug-C guard sliced the QUERY to
num_prefill_tokens under CUDA-graph / MTP-draft padding but passed the UNSLICED
padded OUTPUT to the runner. The flashinfer kernel derives num_tokens from the
query rows and hard-asserts output.size(0) == num_tokens, so a padded output (84)
vs sliced query (83) aborts. The guard comment already said to slice 'output/
indices/scratch' — only output was missed.

Fix: slice output the same way (a view into the same storage; padded tail rows
are never read downstream). No-op in the unpadded case; PREFILL-gate-only (the
default FlashMLA prefill loops over q.shape[0] and has no such assert). 256k is
irrelevant — 32k + small max-num-seqs + MTP reproduces it.
Default-path crash under MTP + ANY top-k/top-p sampling (i.e. ordinary non-greedy
chat traffic): compute_probs_and_sample_next_token (the MTP draft sampler, a noted
duplicate of the main sampler) called apply_top_k_top_p on the bf16 draft-head
logits, but the triton top-k/top-p kernel asserts logits.dtype == torch.float32
(topk_topp_triton.py:881) -> AssertionError -> worker dies -> EngineDeadError.

Greedy requests return early (all_greedy branch) and never reach the sampler, so
greedy-only GSM8K validation never exercised this — a 256k sampled-traffic soak
(temperature 0.7, top_p 0.9) crashes in ~25s. Fix mirrors the main sampler: cast
logits to float32 before div_/apply_top_k_top_p. Likely the (or a) root cause of
the PR#41834 default-path crash reports under real chat traffic.
# Conflicts:
#	vllm/model_executor/warmup/kernel_warmup.py
#	vllm/models/deepseek_v4/nvidia/model.py
#	vllm/utils/deep_gemm.py
#	vllm/utils/flashinfer.py
#	vllm/v1/attention/backends/mla/sparse_swa.py
#	vllm/v1/core/block_pool.py
vllm-project#43477 added family-120 to CudaPlatform.support_deep_gemm, which selects the
DeepGEMM SM120 MXFP4 kernels. Those need the still-unmerged DeepGEMM PR vllm-project#324; the
released/pinned DeepGEMM ref aborts at engine init on SM120 with a scale-factor
layout assertion (sf.size(-2) == ceil_div(mn, gran_mn)), so DSv4 fails to serve
on stock deps. Drop family-120 here so SM120 uses the Marlin/cutlass + sm12x
DeepGEMM-fallback path (matches pre-vllm-project#43477 behavior). Re-enable when vllm-project#324 lands.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
… OOB (inference crash)

Reconciling vllm-project#43477's sparse_swa I dropped the prefill-SWA gate, so
_compute_swa_indices_and_lens_kernel launched unconditionally over all prefill
tokens. Its block_table load computes the address for every lane (only the load
is masked); the masked-off tail lanes of a deep (32k) prefill row index past the
request's block_table row -> cudaErrorLaunchFailure under concurrent load (the
'unspecified launch failure' that wedged SM120). The sibling kernel in this file
already clamps this exact SM12x+Triton-3.6 masked-lane IMA via safe_offset.

The prefill-SWA indices are consumed only by the FlashInfer-SM120 fork attention
path; the stock FlashMLA/Triton prefill self-computes and discards them. Fix:
(1) re-gate the launch + metadata behind VLLM_DEEPSEEK_V4_FLASHINFER_SM120_PREFILL
(default off) -> stock path back to pre-reconcile decode-only behavior;
(2) clamp the masked-off lanes in _compute_swa_indices_and_lens_kernel
(defense-in-depth); (3) pass the now-mandatory token_offset=0 in the
flashinfer_sm120_decode self-compute fallback (latent TypeError).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
kernel_warmup.py imported the removed module constant
_INDEXED_D512_SPLIT_PREFILL_MIN_TOKENS from flashmla.py, which a prior refactor
replaced with envs.VLLM_DEEPSEEK_V4_INDEXED_D512_SPLIT_PREFILL_MIN_TOKENS. The
ImportError was swallowed by the surrounding `except ImportError`, so the
D512-split prefill warmup (default-on for DSv4 SM12x) silently self-skipped: the
first long prefill (>4096 tokens) JIT-compiled the split kernels mid-inference
(latency spike, and a hang/crash on FULL-capture builds at long context),
negating the warmup PR vllm-project#41834 added.

Drop the dead import item and point the max_model_len guard at the env var
(envs is already imported). Also raise the swallowed-import log from DEBUG to
WARNING: the early gate already confirms the warmup was requested, so a failed
import here is a real problem (a renamed symbol) that should surface instead of
no-op'ing for weeks.

Reported, diagnosed, and patched by @wingcomm (PR vllm-project#41834).
Include batch size 3 in _DEEPSEEK_V4_MTP_UNIFORM_DECODE_WARMUP_REQUESTS
to pre-compile sparse-MLA decode attention kernels at that batch shape
during startup warmup.

Without this, 10 Triton JIT kernels in the decode attention path compile
on first use when concurrency climbs to 3, causing ~20s latency spikes:
  _build_combined_decode_valid_mask_kernel
  _finish_materialized_scores_with_sink_candidate_block_kernel
  _indexed_d512_split_{score,stats,value}_kernel
  _accumulate_fp8ds_global_slots_attention_chunk_multihead_kernel
  _finish_two_attention_states_with_sink_kernel
  _indexed_d512_chunked_merge_{acc,state}_kernel
  _accumulate_indexed_attention_chunk_multihead_kernel

Observed on DeepSeek-V4-Flash EP=2 on dual GB10 (SM12x) with 1M context.

cc: jasl PR vllm-project#41834
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@jasl

jasl commented Jun 24, 2026

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I need to validate it this Friday

@erictinkeredapps

erictinkeredapps commented Jun 25, 2026

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DeepSeek-V4-Flash-GB10.yaml

Including our recipe. Has comments / documentation included. We've put some mileage on it at this point - let us know if you need us to look at anything specific.

Appreciate your efforts jasl, Thank you!!

@jasl

jasl commented Jun 26, 2026

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Thanks @lennytinkeredapps — good catch that the warmup tuple (1, 2, 4, 8, 16, 24, 32) skips 3, and the diff is clean (the union logic at kernel_warmup.py does produce (1, 2, 3, 4, 8, 16, 24, 32, 256) for the c256 case, so the test update is internally consistent).

I validated it on our dual-GB10 (SM121) box today with a JIT-coverage gate, and I want to share the result before merging, because it changes what the right fix is.

Gate result: with the baseline warmup (no batch-3), driving concurrency-3 MTP decode produced 0 in-inference JIT compiles of the decode kernels. So on our MTP2 config, batch=3 is not an uncovered shape — there's nothing left to warm.

Here's why, from the decode path:

  • The decode kernels' Triton compile key is batch-independent. num_tokens only feeds the launch grid (grid=(num_tokens, …), token_idx = tl.program_id(0)); Triton does not specialize cubins on grid dims. Every shape constexpr (strides, num_heads, num_candidates, HEAD_DIM, BLOCK_C) is per-token / per-head.
  • The one batch-driven constexpr is HEAD_BLOCK, from sparse_mla_decode_head_block_size(num_decode_tokens) (sparse_mla_kernels.py): 1 for ≤4, 2 for 4 < x < 16, 4 for ≥16. It keys off num_decode_tokens = num_reqs * query_len, not num_reqs. For MTP2 (query_len = 3): num_reqs=2 → 6 tok → HB=2, and num_reqs=3 → 9 tok → HB=2 — the same cubin that num_reqs=2 already warms. So the existing tuple already covers all three HEAD_BLOCK regimes (1/2/4) and both use_dot_finish branches (the ≤16 split).
  • Also, 6 of the 10 kernels you listed (_indexed_d512_split_{score,stats,value}, _indexed_d512_chunked_merge_{acc,state}, _accumulate_indexed_attention_chunk_multihead) are actually prefill kernels — only reached from _forward_sparse_mla_prefill_triton (kv.shape[0] == 1) and warmed by _deepseek_v4_indexed_d512_split_prefill_warmup, not by this decode-tuple edit. So the decode-tuple change can't move those regardless.

So the change is safe and rebases cleanly, but on MTP2 it's a no-op — which means it wouldn't eliminate the ~20 s spike you saw, and I don't want to merge something that looks like a fix but isn't.

The deciding question is your exact config. Could you share:

  1. Your spec-decode setting — num_speculative_tokens (MTP2? something else?), or non-spec decode?
  2. The startup warmup log line (… MTP uniform decode requests=[…], or the equivalent) from your run — that tells us exactly which num_decode_tokens got warmed.

If you're on a query_len where batch=3 lands on a real HEAD_BLOCK boundary (i.e. num_reqs * query_len crosses 4 or 16 at num_reqs=3), then 3 genuinely helps and I'll merge it — though in that case the more robust fix is to make the warmup boundary-aware (guarantee HEAD_BLOCK {1, 2, 4} + the ≤16 dot-finish split for the deployed query_len), which I'm happy to put up as a follow-up. If you're on MTP2 like our gate, the spike is coming from somewhere else and we should chase that instead.

And thanks @erictinkeredapps for attaching DeepSeek-V4-Flash-GB10.yaml — we'll review the recipe and fold anything useful into our canonical GB10 serve config.

@lennytinkeredapps

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jasl — here is the warmup log from our dual-GB10 run:

kernel_warmup.py:583: Warming up DeepSeek V4 sparse MLA attention for
mixed tokens=16, prefill tokens=512, and MTP uniform decode requests=[1, 2, 4, 5].

kernel_warmup.py:642: Warming up DeepSeek V4 MTP spec-decode kernels
for request counts=[1, 2, 4, 5] and 2 draft tokens.

kernel_warmup.py:497: Warming up DeepSeek V4 D512-split sparse-MLA prefill kernels
for combined_topk widths=[256, 384, 512, 640] (heads=32, padded_q_heads=64).

Our warmup tuple is [1, 2, 4, 5], not your (1, 2, 4, 8, 16, 24, 32). At our MTP2 (query_len=3): all four warmup request counts land on HEAD_BLOCK ≤ 2 — we never reach HEAD_BLOCK=4. Your tuple hits it at reqs=6+. That alone could explain why your gate sees zero JIT and ours sees compiles.

The prefill side: our max_num_batched_tokens=512 means chunked prefill works in 512-token slices, and the warmup covers combined_topk widths at exactly that chunk size. Production requests arrive with different prompt lengths → different chunk counts, and we see JIT of _compute_prefill_metadata_kernel, _build_prefill_chunk_metadata_kernel, and the _indexed_d512_* family when the chunk geometry does not match the warmup shape. Your gate at 4096 mnbt gets one big prefill chunk per warmup request — different geometry, no surprise you see zero there either.

So our candidate for the real spike: the warmup tuple does not cover all HEAD_BLOCK regimes, and the 512-token prefill chunking creates shapes the warmup does not exercise. The boundary-aware warmup you offered (guarantee HEAD_BLOCK {1, 2, 4} + dot-finish split for the deployed query_len) plus extending the prefill warmup to cover the actual chunk counts we see in production would be the right fix — and we would be happy to test it.

@jasl jasl force-pushed the codex/ds4-sm120-min-enable branch from 8959fe6 to fd76d65 Compare June 27, 2026 04:56
@jasl

jasl commented Jun 30, 2026

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Sorry, I forgot to ask you that I've improved the warmup in codex/ds4-sm120-min-enable branch, could you try it?

@lennytinkeredapps

lennytinkeredapps commented Jun 30, 2026

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jasl — thanks you! We'll try the codex/ds4-sm120-min-enable branch on our dual-GB10 setup.

Will report back with JIT coverage and gen throughput numbers once we've got it running.

@jasl

jasl commented Jun 30, 2026

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The upstream/main requires a specified NV-forked DeepGEMM dependency, for which you have to patch the Makefile and the unreleased FlashInfer, so it actually doesn't work.

@lennytinkeredapps

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JIT cleared at about 4 minutes after the first request. Gen steady at 37-39 tok/s single-stream, prefix cache at 65%. No new JIT warnings after that last _accumulate_indexed_attention_chunk_multihead_kernel at 13:45.

Four minutes from cold start to clean serving. The old container took 15+. Your expanded warmup plus the upstream fp8 kernel paths cut the JIT tax by nearly 75%.

Logs attached and thank you! Let us know if you want us to test anything else we push the GB10s pretty hard inference wise (we're probably good testers if you need us for future adventures).

startup-logs-through-JIT.txt

@jasl

jasl commented Jun 30, 2026

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JIT cleared at about 4 minutes after the first request. Gen steady at 37-39 tok/s single-stream, prefix cache at 65%. No new JIT warnings after that last _accumulate_indexed_attention_chunk_multihead_kernel at 13:45.

Four minutes from cold start to clean serving. The old container took 15+. Your expanded warmup plus the upstream fp8 kernel paths cut the JIT tax by nearly 75%.

Logs attached and thank you! Let us know if you want us to test anything else we push the GB10s pretty hard inference wise (we're probably good testers if you need us for future adventures).

startup-logs-through-JIT.txt

Thank you! I'll dig your logs tomorrow

@lennytinkeredapps

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Closing — jasl incorporated the warmup feedback in codex/ds4-sm120-min-enable with expanded kernel coverage and updated warmup tuples. We just built and validated the new branch: 4 minutes from cold start to clean serving, 54-57 tok/s at 2 concurrent, JIT tax down 75% from prior builds. Thanks jasl for the collaboration — the merge from upstream/main plus the SM12x fixes is exactly what we needed.

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